Product specifications

ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -39- Device 0 Register Descriptions
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Technologies, Inc.
PCI Bus Control
These registers are normally programmed once at system
initialization time.
Device 0 Offset 70 - PCI Buffer Control (00h)................RW
7 CPU to PCI Post-Write
0 Disable ...................................................default
1 Enable
6 Reserved ........................................ always reads 0
5-4 PCI Master to DRAM Prefetch
00 Always prefetch .....................................default
x1 Never prefetch
10 Prefetch only for Enhance command
3-2 Reserved ........................................ always reads 0
1 Delay Transaction
0 Disable ...................................................default
1 Enable
0 Reserved ........................................ always reads 0
Device 0 Offset 71 - CPU to PCI Flow Control (48h).. RWC
7 Retry Status......................................................RWC
0 No retry occurred ...................................default
1 Retry occurred
6 Retry Timeout Action
0 Retry forever (record status only)
1 Flush buffer or return FFFFFFFFh for reads
.....................................................default
5-4 Retry Count and Retry Backoff
00 Retry 2 times, backoff CPU ...................default
01 Retry 16 times
10 Retry 4 times
11 Retry 64 times
3PCIBurst
0Disable
1 Enable ...................................................default
2 Reserved ........................................ always reads 0
1 Compatible Type#1 Configuration Cycles
0 Disable (fixed AD31).............................default
1 Enable
0 IDSEL Control
0 AD11, AD12..........................................default
1 AD30, AD31
Device 0 Offset 73 - PCI Master Control (00h).............. RW
7 Reserved ........................................always reads 0
6 PCI Master 1-Wait-State Write
0 Zero wait state TRDY# response........... default
1 One wait state TRDY# response
5 PCI Master 1-Wait-State Read
0 Zero wait state TRDY# response........... default
1 One wait state TRDY# response
4WSC#
0 Disable................................................... default
1 Enable
3-1 Reserved ........................................always reads 0
0 PCI Master Broken Timer Enable
0 Disable................................................... default
1 Enable. Force into arbitration when there is no
FRAME# 16 PCICLK’s after the grant.