Product specifications

ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -38- Device 0 Register Descriptions
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Device 0 Offset 6E - ECC Control (00h) .........................RW
7 ECC / EC Mode Select
0 ECC Checking and Reporting................default
1 ECC Checking, Reporting, and Correcting
6 Perform Read-Modify-Write for Partial Write
0 Disable ...................................................default
1 Enable
5 Enable SERR# on ECC / EC Multi-Bit Error
0 Don’t assert SERR# for multi-bit errors .....def
1 Assert SERR# for multi-bit errors
4 Enable SERR# on ECC / EC Single-Bit Error
0 Don’t assert SERR# for single-bit errors .....def
1 Assert SERR# for single-bit errors
3 ECC / EC Enable - Bank 7/6 (DIMM 3)
0 Disable (no ECC or EC for banks 7/6)...default
1 Enable (ECC or EC per bit-7)
2 ECC / EC Enable - Bank 5/4 (DIMM 2)
0 Disable (no ECC or EC for banks 5/4)...default
1 Enable (ECC or EC per bit-7)
1 ECC / EC Enable - Bank 3/2 (DIMM 1)
0 Disable (no ECC or EC for banks 3/2)...default
1 Enable (ECC or EC per bit-7)
0 ECC / EC Enable - Bank 1/0 (DIMM 0)
0 Disable (no ECC or EC for banks 1/0)...default
1 Enable (ECC or EC per bit-7)
Error checking / correction may be enabled bank-pair by bank-
pair (DIMM by DIMM) by using bits 0-3 above. Bank pairs
must be populated with 72-bit memory to enable for EC or
ECC since the additional data bits must be present in either
case. For this reason, if 64-bit memory is populated in a
particular bank pair, the corresponding bit 0-3 should be set to
0 to disable both EC and ECC for that bank pair. For those
bank pairs that have 72-bit memory available (and have the
corresponding bit 0-3 set), either EC or ECC may be selected
via bit-7 above (i.e., all enabled bank pairs will use EC or all
will use ECC).
If error checking / reporting only (EC) is selected, all read and
write cycles will use normal timing. Partial writes (with EC or
ECC enabled) will use read-modify-write cycles to maintain
correct error correction codes in the additional 8 data bits. If
EC and ECC are disabled for a particular bank pair, partial
writes to that bank pair will use the byte enables to write only
the selected bytes (using normal write cycles and cycle
timing). If error correction (ECC) is selected, the first read of
a transaction will always have one additional cycle of latency.
Bit-7
Bits 3-0 RMW Error Checking Error Correction
0/1 0 No No No
0 1 Yes Yes No
1 1 Yes Yes Yes
Device 0 Offset 6F - ECC Status (00h)..........................RWC
7 Multi-bit Error Detected .............. write of ‘1’ resets
6-4 Multi-bit Error DRAM Bank....................default=0
Encoded value of the bank with the multi-bit error.
3 Single-bit Error Detected ............. write of ‘1’ resets
2-0 Single-bit Error DRAM Bank .................. default=0
Encoded value of the bank with the single-bit error.
Table 9. DIMM Module Configuration
Rx6B Rx6E Rx6E Rx55
[4] [3-0] [6] [3] DIMM MECC DQM DQS#
CKE ECC RMW No Module [7-0] [8-0] [8-0]
Ena
Ena Ena DQM Configuration Pins Pins Pins
1 1 1 1 DDR Only x4 with ECC MECC[7-0] CKE[7-0] DQS[8-0]#
1 1 0 1 DDR Only x8 with ECC MECC[7-0] CKE[7-0] DQS[8-0]#
1 0 0 0 DDR Only x8 no ECC CKE[7-0] DQM[7-0] DQS[7-0]#
0 0 0 0 184-Pin DDR/SDR Mix CKE[7-0] DQM[8-0] DQS[8-0]#
1 1 x 0 168-Pin SDR Only MECC[7-0] DQM[8-0] CKE[7-0]
1 0 0 1 2 DDR + 2 SDR (SDR Installed) CKE[7-0] - DQS[7-0]#
1 0 0 0 2 DDR + 2 SDR (DDR Installed) CKE[7-0] DQM[7-0] DQS[7-0]#