Product specifications

ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge

Revision 1.1, July 19, 2002 -37- Device 0 Register Descriptions

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Technologies, Inc.

Device 0 Offset 6C – DRAM Drive Control 1 (00h) .......RW

7-6 SDRAM A Drive – SRASA/SCASA/SWEA, MAA

00 Lowest....................................................default

11 Highest

5-4 SDRAM B Drive – SRASB/SCASB/SWEB, MAB

00 Lowest....................................................default

11 Highest

3-2 DDR DQS Drive

00 Lowest....................................................default

11 Highest

1-0 MD/MECC/DQM/CKE Early Clock Select

00 Latest .....................................................default

11 Earliest

Note: Refer to the VT8751 BIOS Porting Guide for SDRAM

configuration algorithms and recommended settings for these

bits for typical memory system configurations.

Device 0 Offset 6D – DRAM Drive Control 2 (00h)....... RW

7-6 Early Clock Select for SCMD, MA Output (for 1T

Command)

00 Latest .................................................... default

11 Earliest

5-4 DQM Drive

00 Lowest ................................................... default

11 Highest

3-2 CS# Drive

00 Lowest ................................................... default

11 Highest

1-0 Memory Data Drive (MD, MECC)

00 Lowest ................................................... default

11 Highest

Note: Refer to the VT8751 BIOS Porting Guide for SDRAM

configuration algorithms and recommended settings for these

bits for typical memory system configurations.