Product specifications

ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -36- Device 0 Register Descriptions
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Technologies, Inc.
Device 0 Offset 69 – DRAM Clock Select (00h)..............RW
7 CPU Operating Frequency Faster Than DRAM
0 CPU Same As or Equal to DRAM.........default
1 CPU Faster Than DRAM by 33 MHz
6 DRAM Operating Frequency Faster Than CPU
0 DRAM Same As or Equal to CPU.........default
1 DRAM Faster Than CPU by 33 MHz
Bits
7-6 CPU / DRAM
10 100 / 66
00 100 / 100..........................................default
01 100 / 133
5S1Resume
0 Compatible.............................................default
1 Enhanced
4 DRAM Controller Queue Not Equal to 4
0 Disable ...................................................default
1 Enable
3 DRAM 8K Page Enable
0 Disable ...................................................default
1 Enable
2 DRAM 4K Page Enable
0 Disable ...................................................default
1 Enable
1DIMMType
0 Unbuffered .............................................default
1 Registered
0 Multiple Page Mode
0 Disable ...................................................default
1 Enable
Device 0 Offset 6A - Refresh Counter (00h)................... RW
7-0 Refresh Counter (in units of 16 MCLKs)
00 DRAM Refresh Disabled ...................... default
01 32 MCLKs
02 48 MCLKs
03 64 MCLKs
04 80 MCLKs
05 96 MCLKs
……
The programmed value is the desired number of 16-
MCLK units minus one.
Device 0 Offset 6B - DRAM Arbitration Control (10h) RW
7 Fast Read to Write Turn-around
0 Disable................................................... default
1 Enable
6 Page Kept Active When Cross Bank
0 Disable................................................... default
1 Enable
5 Burst Refresh
0 Disable................................................... default
1 Enable
4 CKE Function
0Disable
1 Enable ................................................... default
3 HA14/HA22Swap
0 Normal................................................... default
1 Swap to improve performance
2-0 SDRAM Operation Mode Select
000 Normal SDRAM Mode ......................... default
001 NOP Command Enable
010 All-Banks-Precharge Command Enable
(CPU-to-DRAM cycles are converted
to All-Banks-Precharge commands).
011 MSR Enable
CPU-to-DRAM cycles are converted to
commands and the commands are driven on
MA[14:0]. The BIOS selects an appropriate
host address for each row of memory such that
the right commands are generated on
MA[14:0].
100 CBR Cycle Enable (if this code is selected,
CAS-before-RAS refresh is used; if it is not
selected, RAS-Only refresh is used)
101 Reserved
11x Reserved