Product specifications

ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -35- Device 0 Register Descriptions
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Technologies, Inc.
Device 0 Offset 64 - DRAM Timing for All Banks (E4h)RW
7 Precharge Command to Active Command Period
0T
RP =2T
1T
RP =3T................................................default
6 Active Command to Precharge Command Period
0T
RAS =5T
1T
RAS =6T..............................................default
5-4 CAS Latency
SDR
DDR
00 1T -
01 2T 2T
10 3T 2.5T...........................................default
11 - 3T
3 Reserved ........................................ always reads 0
2 ACTIVE to CMD
02T
13T ....................................................default
1-0 Bank Interleave
00 No Interleave..........................................default
01 2-way
10 4-way
11 Reserved
For 16Mb SDRAMs bank interleave is always 2-way
Device 0 Offset 65 - DRAM Arbitration Timer (00h) ....RW
7-4 AGP Timer (units of 4 MCLKs) .............. default = 0
3-0 CPU Timer (units of 4 MCLKs)............... default = 0
Device 0 Offset 66 - DRAM Arbitration Control (00h)..RW
7 SDR – Feedback Clock Select
DDR - DQS Input Delay Setting
0 Auto (Rx67 reads DLL calibration result) ...def
1 Manual (Rx67 reads DQS input delay)
6 DRAM Access Timing
0 2T .....................................................default
1 3T (Set this bit for 133 MHz DRAM clock)
5-4 Arbitration Parking Policy
00 Park at last bus owner ............................default
01 Park at CPU
10 Park at AGP
11 -reserved-
3-0 AGP / CPU Priority (units of 4 MCLKs)
Device 0 Offset 67 – DDR Strobe Input Delay (00h) ..... RW
DDR:
7-6 CS Early Clock Select .............................. default = 0
5-0 DQS Input Delay ...................................... default = 0
(if Rx66[7]=0, read DLL calibration result)
SDR:
7-5 Reserved ........................................always reads 0
4 MD Latch Clock Select
0 Internal clock......................................... default
1 External feedback clock
3 Reserved ........................................always reads 0
2-0 MD Latch Delay
Device 0 Offset 68 – DDR Strobe Output Delay (00h)... RW
7-0 DDR DQS Output Delay ......................... default = 0