Product specifications
ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -ii- Table of Contents
We Connect
We ConnectWe Connect
We Connect
Technologies, Inc.
TABLE OF CONTENTS
REVISION HISTORY .......................................................................................................................................................................I
TABLE OF CONTENTS.................................................................................................................................................................. II
LIST OF FIGURES .........................................................................................................................................................................IV
LIST OF TABLES ...........................................................................................................................................................................IV
PRODUCT FEATURES.................................................................................................................................................................... 1
OVERVIEW....................................................................................................................................................................................... 4
H
IGH-PERFORMANCE 3D ACCELERATOR.................................................................................................................................... 5
128-
BIT 2D GRAPHICS ENGINE ..................................................................................................................................................... 5
DVD P
LAYBACK AND VIDEO CONFERENCING ............................................................................................................................. 5
F
LAT PANEL MONITOR /TVOUT SUPPORT ................................................................................................................................5
H
IGH SCREEN RESOLUTION CRT SUPPORT ................................................................................................................................6
PINOUTS............................................................................................................................................................................................ 7
PIN DESCRIPTIONS...................................................................................................................................................................... 10
REGISTERS..................................................................................................................................................................................... 20
R
EGISTER OVERVIEW ................................................................................................................................................................. 20
M
ISCELLANEOUS I/O .................................................................................................................................................................. 24
C
ONFIGURATION SPACE I/O ....................................................................................................................................................... 24
D
EVICE 0REGISTER DESCRIPTIONS........................................................................................................................................... 25
Device 0 Host Bridge Header Registers .............................................................................................................................. 25
Device 0 Host Bridge Device-Specific Registers................................................................................................................. 27
V-Link Control...................................................................................................................................................................................... 27
Host CPU Control ................................................................................................................................................................................. 30
DRAM Control ..................................................................................................................................................................................... 32
PCI Bus Control.................................................................................................................................................................................... 39
GART / Graphics Aperture Control ...................................................................................................................................................... 41
AGP Control ......................................................................................................................................................................................... 42
AGP Control (continued) ...................................................................................................................................................................... 43
V-Link Control...................................................................................................................................................................................... 44
DRAM Interface Control ...................................................................................................................................................................... 45
Power Management............................................................................................................................................................................... 45
ECC Error Control ................................................................................................................................................................................ 45
AGTL+ I/O Control .............................................................................................................................................................................. 46
Frame Buffer and High Memory Control.............................................................................................................................................. 47
BIOS Scratch ........................................................................................................................................................................................ 47
DEVICE 1REGISTER DESCRIPTIONS........................................................................................................................................... 48
Device 1 PCI-to-PCI Bridge Header Registers .................................................................................................................. 48
Device 1 PCI-to-PCI Bridge Device-Specific Registers ..................................................................................................... 50
AGP Bus Control .................................................................................................................................................................................. 50
FUNCTIONAL DESCRIPTION - INTEGRATED SAVAGE4 GRAPHICS............................................................................. 53
C
ONFIGURATION STRAPPING ...................................................................................................................................................... 53
PCI C
ONFIGURATION AND INTEGRATED AGP .......................................................................................................................... 53