Product specifications
ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -33- Device 0 Register Descriptions
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Technologies, Inc.
Device 0 Offset 59-58 - DRAM MA Map Type (2222h) .RW
15-13 Bank 5/4 MA Map Type (see table below)
12 Bank 5/4 1T Command Rate
0 2T Command .........................................default
1 1T Command
11-9 Bank 7/6 MA Map Type (see table below)
8 Bank 7/6 1T Command Rate
0 2T Command .........................................default
1 1T Command
7-5 Bank 1/0 MA Map Type (see table below)
4 Bank 1/0 1T Command Rate
0 2T Command .........................................default
1 1T Command
3-1 Bank 3/2 MA Map Type (see table below)
0 Bank 3/2 1T Command Rate
0 2T Command .........................................default
1 1T Command
Table 7. Device 0 Rx58 MA Map Type Encoding
000 16Mb 8-bit, 9-bit, 10-bit Column Address
001 64/128Mb
8-bit Column Address ...................default
010 64/128Mb
9-bit Column Address
011 64/128Mb
10/11-bit Column Address
100 -reserved-
101 256Mb
8-bit Column Address
110 256Mb
9-bit Column Address
111 256Mb
10/11-bit Column Address
Device 0 Offset 5F-5A – DRAM Row Ending Address:
Offset 5A – Bank 0 Ending (HA[31:24]) (01h).......... RW
Offset 5B – Bank 1 Ending (HA[31:24]) (01h) .......... RW
Offset 5C – Bank 2 Ending (HA[31:24]) (01h).......... RW
Offset 5D – Bank 3 Ending (HA[31:24]) (01h).......... RW
Offset 5E – Bank 4 Ending (HA[31:24]) (01h) .......... RW
Offset 5F – Bank 5 Ending (HA[31:24]) (01h) .......... RW
Offset 56 – Bank 6 Ending (HA[31:24]) (01h)........... RW
Offset 57 – Bank 7 Ending (HA[31:24]) (01h)........... RW
Note : BIOS is required to fill the ending address registers
for all banks even if no memory is populated. The endings
have to be in incremental order.
Device 0 Offset 60 – DRAM Type (00h).......................... RW
7-6 DRAM Type for Bank 7/6
5-4 DRAM Type for Bank 5/4
3-2 DRAM Type for Bank 3/2
1-0 DRAM Type for Bank 1/0
00 SDR SDRAM........................................ default
01 -reserved- (do not program)
10 DDR SDRAM
11 -reserved-
Table 8. Memory Address Mapping Table
SDR / DDR SDRAM (x4 DRAMs supported by SDR only)
MA: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
16Mb
(000)
24 13
13
12
PC
11
24
14
23
22
10
21
9
20
8
19
7
18
6
17
5
16
4
15
3
12 row
10,9,8 col
64/128Mb
2K page
001
4K page
010
8K page
011
14
14
14
24
27
25
27
26
27
14
14
14
14
14
14
13
13
13
13
13
13
12
PC
12
PC
25
PC
11
26
24
26
24
12
23
25
23
11
23
11
22
10
22
10
22
10
21
9
21
9
21
9
20
8
20
8
20
8
19
7
19
7
19
7
18
6
18
6
18
6
17
5
17
5
17
5
16
4
16
4
16
4
15
3
15
3
15
3
x16 (14,8)
x32 (14,8)
x8 (14,9)
x16 (14,9)
x4 (14,10)
x8 (14,10)
x4 (14,11)
256Mb
2K page
101
4K page
110
8K page
111
25
26
27
24
27
25
27
26
28
14
14
14
14
14
14
13
13
13
13
13
13
12
PC
12
PC
25
PC
11
26
24
26
24
12
23
25
23
11
23
11
22
10
22
10
22
10
21
9
21
9
21
9
20
8
20
8
20
8
19
7
19
7
19
7
18
6
18
6
18
6
17
5
17
5
17
5
16
4
16
4
16
4
15
3
15
3
15
3
x32 (15,8)
x16 (15,9)
x8 (15,10)
x4 (15,11)