Product specifications

ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge

Revision 1.1, July 19, 2002 -32- Device 0 Register Descriptions

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DRAM Control

These registers are normally set at system initialization time

and not accessed after that during normal system operation.

Some of these registers, however, may need to be programmed

using specific sequences during power-up initialization to

properly detect the type and size of installed memory (refer to

the VIA Technologies VT8751 BIOS porting guide for

details).

Table 6. System Memory Map

Space Start Size Address Range Comment

DOS 0 640K 00000000-0009FFFF Cacheable

VGA 640K 128K 000A0000-000BFFFF Used for SMM

BIOS 768K 16K 000C0000-000C3FFF Shadow Ctrl 1

BIOS 784K 16K 000C4000-000C7FFF Shadow Ctrl 1

BIOS 800K 16K 000C8000-000CBFFF Shadow Ctrl 1

BIOS 816K 16K 000CC000-000CFFFF Shadow Ctrl 1

BIOS 832K 16K 000D0000-000D3FFF Shadow Ctrl 2

BIOS 848K 16K 000D4000-000D7FFF Shadow Ctrl 2

BIOS 864K 16K 000D8000-000DBFFF Shadow Ctrl 2

BIOS 880K 16K 000DC000-000DFFFF Shadow Ctrl 2

BIOS 896K 64K 000E0000-000EFFFF Shadow Ctrl 3

BIOS 960K 64K 000F0000-000FFFFF Shadow Ctrl 3

Sys 1MB — 00100000-DRAM Top Can have hole

Bus D Top DRAM Top-FFFEFFFF

Init 4G-64K 64K FFFEFFFF-FFFFFFFF 000Fxxxx alias

Device 0 Offset 55 – DRAM Control (00h)..................... RW

7 0WS Back-to-Back Write to Different DDR Bank