Product specifications

ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -31- Device 0 Register Descriptions
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Device 0 Offset 52 – CPU Interface Advanced Ctrl (00h)RW
7 CPU RW DRAM 0WS for Back-to-Back Pipeline
Access
0 Disable ...................................................default
1 Enable
6 HREQ High Priority
0 Disable ...................................................default
1 Enable
5C2P2Timing
0 Compatible.............................................default
1 Enhanced
This bit should always be set to 1.
4 Dynamic Snoop Stall for CPU FIFO Full
0 Disable ...................................................default
1 Enable
3 Write Retire Policy After 2 Writes
0 Disable ...................................................default
1 Enable
2 133 / 100 DADS Fast Conversion
0 Disable ...................................................default
1 Enable
1 Consecutive Speculative Read
0 Disable ...................................................default
1 Enable
0 Speculative Read
0 Disable ...................................................default
1 Enable
Device 0 Offset 53 – CPU Arbitration Control (03h) .....RW
7-4 Host Timer .............................................. default = 0
3-0 BPRI Timer (units of 4 HCLKs) .............. default = 3
Device 0 Offset 54 – CPU Frequency (00h) .................... RW
7-6 CPU Clock Frequency .....Set from VAD1-0 Straps
00 66 MHz
01 100 MHz
10 Auto
1 133 MHz
5 Auto Configure (ROMSIP) . Set from VAD6 Strap
0 Disable (strap pulled low). Chip configuration
settings per on-chip defaults.
1 Enable (strap pulled high). AGTL+ Drive
settings and other chip configuration settings
are stored in ROM, transferred from the south
bridge (via the V-Link bus), and loaded into
the VT8703 automatically after system reset.
Refer to the VT8703 BIOS Porting Guide for
layout of the AutoConfigure settings in ROM
and for recommended bit settings.
4 SDRAM Burst Length of 8
0 Disable................................................... default
1 Enable
3 Reserved ........................................always reads 0
2 PCI Master 8QW Operation
0 Disable................................................... default
1 Enable
1 AGP Capability Header Support
0 Disable................................................... default
1 Enable
0 Reserved ........................................always reads 0