Product specifications

ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -30- Device 0 Register Descriptions
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Technologies, Inc.
Host CPU Control
Device 0 Offset 50 – Request Phase Control (00h) .........RW
7 CPU Hardwired IOQ (In Order Queue) Size....RO
Default set from the inverse of the VAD2 (south
bridge SA18) strap. E.g., this bit can be strapped 0
(strap pin pulled high) to restrict the chip to one level
of IOQ.
0 1-Level (strap pin pulled high)
1 8-Level (strap pin pulled low)
6 AGTL+ Pullups
Default set from the inverse of the VAD3 (south
bridge SA19) strap.
0 Disable (strap pulled high)
1 Enable (strap pulled low)
5 Fast DRAM Access
0 Disable ...................................................default
1 Enable
4-0 Dynamic Defer Snoop Stall Count
(granularity = 2T, normally set to 01000b)
Device 0 Offset 51 – CPU Interface Basic Control (00h)RW
7 CPU Read DRAM Fast Ready
0 Medium / Slow Ready (see bit 0) .......... default
1 Fast Ready (bit-0 of this register is ignored)
6 Read Around Write
0 Disable................................................... default
1 Enable
5 DRQ Control
0 Non pipelined similar to VT8633.......... default
1 Pipelined
4 CPU to PCI Read Defer
0 Disable................................................... default
1 Enable
3 Two Defer / Retry Entries
0 Disable................................................... default
1 Enable
2 Two Defer / Retry Entries Shared
0 Each entry is dedicated to 1 CPU .......... default
1 Each entry is shared by 2 CPUs
1 PCI Master Pipelined Access
0 Disable................................................... default
1 Enable
0 CPU Read DRAM Ready
(this bit is ignored if bit-7 = 1)
0 Slow .................................................... default
1Medium