Product specifications

ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -26- Device 0 Register Descriptions
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Device 0 Host Bridge Header Registers (continued)
Device 0 Offset E - Header Type (00h).............................RO
7-0 HeaderTypeCode............. reads 00: single function
Device 0 Offset F - Built In Self Test (BIST) (00h)..........RO
7 BIST Supported .......reads 0: no supported functions
6-0 Reserved ........................................ always reads 0
Device 0 Offset 13-10 - Graphics Aperture Base
(00000008h) .......................................................................RW
31-28 Upper Programmable Base Address Bits ...... def=0
27-20 Lower Programmable Base Address Bits ...... def=0
These bits behave as if hardwired to 0 if the
corresponding Graphics Aperture Size register bit
(Device 0 Offset 84h) is 0.
27 26 25 24 23 22 21 20 (This Register)
7
6 5 4 3 2 1 0 (GrAperSize)
RW RW RW RW RW RW RW RW 1M
RW RW RW RW RW RW RW 0 2M
RW RW RW RW RW RW 0 0 4M
RW RW RW RW RW 0 0 0 8M
RW RW RW RW 0 0 0 0 16M
RWRWRW00000 32M
RWRW000000 64M
RW0000000 128M
00000000 256M
19-0 Reserved ................................ always reads 00008
Note: The locations in the address range defined by this
register are prefetchable.
Device 0 Offset 2D-2C – Subsystem Vendor ID (0000h)R/W1
15-0 Subsystem Vendor ID .............................. default = 0
This register may be written once and is then read only.
Device 0 Offset 2F-2E – Subsystem ID (0000h)........... R/W1
15-0 Subsystem ID............................................ default = 0
This register may be written once and is then read only.
Device 0 Offset 37-34 - Capability Pointer (000000A0h) RO
Contains an offset from the start of configuration space.
31-0 AGP Capability List Pointer ........always reads A0h