Product specifications

ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -23- Register Summary Tables
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Technologies, Inc.
P4M266 Device 1 Registers - PCI-to-PCI Bridge
Header Registers
Offset
Configuration Space Header Default Acc
1-0 Vendor ID
1106
RO
3-2 Device ID
B091
RO
5-4 Command
0007 RW
7-6 Status
0230 WC
8 Revision ID
nn
RO
9 Program Interface 00 RO
A Sub Class Code
04
RO
B Base Class Code
06
RO
C -reserved- 00 —
D Latency Timer 00 RO
E Header Type
01
RO
F Built In Self Test (BIST) 00 RO
10-17 -reserved- 00 —
18 Primary Bus Number 00
RW
19 Secondary Bus Number 00
RW
1A Subordinate Bus Number 00
RW
1B Secondary Latency Timer 00 RO
1C I/O Base
F0 RW
1D I/O Limit 00
RW
1F-1E Secondary Status 0000 RO
21-20 Memory Base
FFF0 RW
23-22 Memory Limit (Inclusive) 0000
RW
25-24 Prefetchable Memory Base
FFF0 RW
27-26 Prefetchable Memory Limit 0000
RW
28-33 -reserved- 00 —
34 Capability Pointer
80
RO
35-3D -reserved- 00 —
3F-3E PCI-to-PCI Bridge Control 00
RW
Device-Specific Registers
Offset
AGP Bus Control Default Acc
40 CPU-to-AGP Flow Control 1 00 RW
41 CPU-to-AGP Flow Control 2
08
RW
42 AGP Master Control 00 RW
43 AGP Master Latency Timer
43
RW
44 Reserved (Do Not Program) 00 RW
45 Fast Write Control
72
RW
47-46 PCI-to-PCI Bridge Device ID 0000 RW
48-7F -reserved- 00 —
80 Capability ID
01 RO
81 Next Pointer 00
RO
82 Power Management Capabilities 1
02 RO
83 Power Management Capabilities 2 00
RO
84 Power Management Control / Status 00 RW
85 Power Management Status 00
RO
86 PCI-PCI Bridge Support Extensions 00
RO
87 Power Management Data 00
RO
88-FF -reserved- 00 —