Product specifications
ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -21- Register Summary Tables
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Technologies, Inc.
P4M266 Device 0 Registers - Host Bridge
Header Registers
Offset
Configuration Space Header Default Acc
1-0 Vendor ID
1106
RO
3-2 Device ID
3148
RO
5-4 Command
0006 RW
7-6 Status
0210 WC
8 Revision ID
0n
RO
9 Program Interface 00 RO
A Sub Class Code 00 RO
B Base Class Code
06
RO
C -reserved- 00 —
D Latency Timer 00
RW
E Header Type 00 RO
F Built In Self Test (BIST) 00 RO
13-10 Graphics Aperture Base
0000 0008 RW
14-2B -reserved- 00 —
2D-2C Subsystem Vendor ID 0000
W1
2F-2E Subsystem ID 0000
W1
30-33 -reserved- 00 —
37-34 Capability Pointer
0000 00A0
RO
38-3F -reserved- 00 —
Device-Specific Registers
Offset
V-Link Control Default Acc
40 V-Link Revision ID 00
RO
41 V-Link NB Capability
18 RO
42 V-Link NB Downlink Command
88
RW
44-43 V-Link NB Uplink Status
8280 RO
45 V-Link NB Bus Timer
44
RW
46 V-Link Misc NB Control 00 RW
47 V-Link Control 00 RW
48 V-Link NB/SB Configuration
18
RW
49 V-Link SB Capability
18 RO
4A V-Link SB Downlink Status
88 RO
4C-4B V-Link SB Uplink Command
8280
RW
4D V-Link SB Bus Timer
44
RW
4E CCA Master High Priority 00 RW
4F V-Link SB Miscellaneous Control 00 RW
Offset Host CPU Protocol Control Default Acc
50 CPU Interface Request Phase Control 00 RW
51 CPU Interface Basic Control 00 RW
52 CPU Interface Advanced Control 00 RW
53 CPU Interface Arbitration Control
03
RW
54 CPU Frequency 00 RW
Device-Specific Registers (continued)
Offset
DRAM Control Default Acc
55 DRAM Control 00 RW
56-57 (see below)
59-58 MA Map Type
2222
RW
5F-5A DRAM Row Ending Address:
5A Bank 0 Ending (HA[31:24])
01
RW
5B Bank 1 Ending (HA[31:24])
01
RW
5C Bank 2 Ending (HA[31:24])
01
RW
5D Bank 3 Ending (HA[31:24])
01
RW
5E Bank 4 Ending (HA[31:24])
01
RW
5F Bank 5 Ending (HA[31:24])
01
RW
56
Bank 6 Ending (HA[31:24])
01
RW
57
Bank 7 Ending (HA[31:24])
01
RW
60 DRAM Type 00 RW
61 ROM Shadow Control C0000-CFFFF 00 RW
62 ROM Shadow Control D0000-DFFFF 00 RW
63 ROM Shadow Control E0000-FFFFF 00 RW
64 DRAM Timing for All Banks
E4
RW
65 DRAM Arbitration Timer 00 RW
66 DRAM Arbitration Control 00 RW
67 DRAM DQS/SDR/MD Read Delay 00 RW
68 DRAM DDR Control 00 RW
69 DRAM Clock Select 00 RW
6A DRAM Refresh Counter 00 RW
6B DRAM Arbitration Control
10
RW
6C DRAM Drive Control 1 00 RW
6D DRAM Drive Control 2 00 RW
6E ECC Control 00 RW
6F ECC Status 00
WC
Offset PCI Bus Control Default Acc
70 PCI Buffer Control 00 RW
71 CPU to PCI Flow Control 48
WC
72 -reserved- 00 —
73 PCI Master Control 00 RW
74 -reserved- 00 —
75 PCI Arbitration 1 00 RW
76 PCI Arbitration 2 00 RW
77-7D -reserved- 00 —
7E-7F Reserved (do not program) 00 RW