Product specifications

ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -18- Pin Descriptions
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Configuration Straps
Signal Name Pin # I/O Signal Description
Strap / FPD9 / TVD9,
Strap / FPD7 / TVD7,
Strap / FPD6 / TVD6,
Strap / FPD5 / TVD5,
Strap / FPD4 / TVD4,
Strap / FPD3 / TVD3,
Strap / FPD2 / TVD2,
Strap / FPD1 / TVD1,
Strap / FPD0 / TVD0
E12
A12
C12
D12
E13
D13
A13
B13
C13
I
Straps.
Strap
Strap Name Definition (L=low, H=high) Register
FPD9 Graphics Test Mode L=Disable, H=Enable
FPD7-4 Panel Type OEM Defined CRF0[3:0]
FPD3 XDCLK clock input on XIN L=Disable, H=Enable CR37[3]
FPD2 PCI Base Address Mapping L=Map0, H=Map1 CRB0[7]
FPD1 I/O Disable L=Enable, H=Disable CR36[4]
FPD0 PCI Interrupt Disable L=Enable, H=Disable CR36[0]
(for more information on straps, see Table 11 in the Functional Description section
of this document)
Reference Voltages
Signal Name Pin # I/O Signal Description
GTLVREF
L24 P Host CPU Interface AGTL+ Voltage Reference. 2/3 VTT ±2% typically derived
using a resistive voltage divider. See P4M266 Design Guide.
HDVREF
F16, F19,
F22, F24
P Host CPU Data Voltage Reference. 2/3 VTT ±2% typically derived using a
resistive voltage divider. See P4M266 Design Guide.
HAVREF
R24, V24 P Host CPU Address Voltage Reference. 2/3 VTT ±2% typically derived using a
resistive voltage divider. See P4M266 Design Guide.
HCMPVREF
G24 P Host CPU Compensation Voltage Reference. 1/3 VTT ±2% typically derived
using a resistive voltage divider. See P4M266 Design Guide.
MEMVREF
AD7, AD12,
AD18, AD23
P Memory Voltage Reference. 1/2 VCC25 ±2% typically derived using a resistive
voltage divider. See P4M266 Design Guide.
VLVREF
Y5 P V-Link Voltage Reference. 0.9V derived using a resistive voltage divider
consisting of 2K Ω 1% to VCC25 and 1.13K Ω 1% to ground.
AGPVREF
G6, R6 P AGP Voltage Reference. 0.4 VCCQQ (1.32V) when VCCQQ is 3.3V and 0.5
VCCQQ (0.75V) when VCCQQ is 1.5V. Check the VT8751 Design Guide for
additional information.
Compensation
Signal Name Pin # I/O Signal Description
HRCOMP
F25 AI Host CPU Compensation. Connect 20.5Ω 1% resistor to ground. Used for Host
CPU interface I/O buffer calibration.
VLCOMP
AB4 AI Vlink P-Channel Compensation. Connect 70Ω 1% resistor to ground.
GCOMPN0
A2 AI
AGP N-Channel Compensation 0.
GCOMPN1
B3 AI
AGP N-Channel Compensation 1.