Product specifications

ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -17- Pin Descriptions
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Clocks, Resets, Power Control, General Purpose I/O, Interrupts and Test
Signal Name Pin # I/O Signal Description
HCLK
N25 I Host Clock. This pin receives the host CPU clock (100 MHz). This clock is used by all
P4M266 logic that is in the host CPU domain.
HCLK#
M25 I Host Clock Complement. Used for Quad Data Transfer on host CPU bus.
MCLK
AC25 O Memory (SDRAM) Clock. Output from internal clock generator to the external clock
buffer.
MCLKF
AD25 I Memory (SDRAM) Clock Feedback. Input from the external clock buffer.
DCLKI
C8 I Dot Clock (Pixel Clock) In. Used for external EMI reduction circuit if used. Connect
to GND if external EMI reduction circuit not implemented.
DCLKO
D8ODot Clock (Pixel Clock) Out. Used for external EMI reduction circuit if used. NC if
external EMI reduction circuit not implemented.
GCLK
U5 I Graphics Clock. Clock for internal graphics controller logic.
XIN /XDCLK A7 I Reference Frequency Input. External 14.31818 MHz clock source. All internal
graphics controller clocks are synthesized on chip using this frequency as a reference.
This pin may also be used as a direct external pixel clock input for the internal graphics
controller, bypassing the on-chip graphics clock synthesizers (for more information, see
the FPD3 pin strap description, graphics controller register CR37[3], and Table 11 in the
Functional Description section of this document).
RESET#
AC3 I Reset. Input from the South Bridge chip. When asserted, this signal resets P4N266 and
sets all register bits to the default value. The rising edge of this signal is used to sample
all power-up strap options Internally puled up.
PWROK
AC1 I Power OK. Connect to South Bridge and Power Good circuitry.
SUSST#
AC4 I Suspend Status. For implementation of the Suspend-to-DRAM feature. Connect to an
external pullup to disable. Internally pulled up.
GPOUT
D11 O General Purpose Output. This pin reflects the state of SRD[0].
GOP0 / XECLK E10 O General Output Port. When SR1A[4] is cleared, this pin reflects the state of CR5C[0].
This pin may also be used as a direct external clock input for the internal graphics
controller (for more information, see the FPD3 pin strap description, graphics controller
register CR37[3], and Table 11 in the Functional Description section of this document).
INTA#
A9 O Interrupt. PCI interrupt output (handled by the interrupt controller in the South Bridge)
BISTIN#
B9 I BIST In. This pin is used for testing and must be tied high (connected to 3.3V) on all
board designs.
TESTIN#
W25 I Test In. This pin is used for testing and must be left unconnected or tied high on all
board designs.
XDCLK /XIN A7 I External DCLK. Used for test of the on-chip Graphics Controller subsystem.
XECLK / GOP0 E10 I External ECLK. Used for test of the on-chip Graphics Controller subsystem.
NC
A1, F2,
M5, AD8,
AE8
–
No Connect.