Product specifications

ProSavageDDR P4M266 VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -16- Pin Descriptions
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Technologies, Inc.
Flat Panel Monitor (DVI) Interface
Signal Name Pin # I/O Signal Description
FPD11 /TVBL#,
FPD10 / TVD10,
FPD9 /TVD9/strap,
FPD8 /TVD8,
FPD7 /TVD7/strap,
FPD6 /TVD6/strap,
FPD5 /TVD5/strap,
FPD4 /TVD4/strap,
FPD3 /TVD3/strap,
FPD2 /TVD2/strap,
FPD1 /TVD1/strap,
FPD0 /TVD0/strap
A11
B11
E12
B12
A12
C12
D12
E13
D13
A13
B13
C13
O
Panel Data. 8mA is the default. 16mA is selected via SR3D[6]=1. This function is
selected on these pins when SR31[4] = 1.
FPCLK /TVCLKO E11 O Panel Clock. 8mA is the default. 16mA may also be selected.
FPHS / TVHS D10 O
Panel Horizontal Sync.
FPVS / TVVS C10 O
Panel Vertical Sync.
FPDE /TVCLKI B10 O
Panel Data Enable.
FPDET / TVD11 A10 I Panel Detect. If SR30[1]=0, SR30[2] will read 1 if a Flat Panel is appropriately
connected. Must be tied to ground if not used.
TV Encoder Interface
Signal Name Pin # I/O Signal Description
TVD11 / FPDET,
TVD10 / FPD10,
TVD9 / FPD9 / strap,
TVD8 / FPD8,
TVD7 / FPD7 / strap,
TVD6 / FPD6 / strap,
TVD5 / FPD5 / strap,
TVD4 / FPD4 / strap,
TVD3 / FPD3 / strap,
TVD2 / FPD2 / strap,
TVD1 / FPD1 / strap,
TVD0 / FPD0 / strap
A10
B11
E12
B12
A12
C12
D12
E13
D13
A13
B13
C13
O
TV Encoder Output Data.
TVCLKI / FPDE B10 I TV Encoder Clock In. Input clock from encoder.
TVCLKO / FPCLK E11 O TV Encoder Clock Out. Output clock to TV encoder.
TVHS / FPHS D10 O
TV Encoder HSYNC.
TVVS / FPVS C10 O
TV Encoder VSYNC.
TVBL# / FPD11 A11 O
TV Encoder Blanking.