Product specifications
ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -14- Pin Descriptions
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AGP Bus Interface (continued)
Signal Name Pin # I/O Signal Description
GRBF#
H5 I Read Buffer Full. Indicates if the master (graphics controller) is ready to
accept previously requested low priority read data. When GRBF# is asserted,
the VT8753 will not return low priority read data to the graphics controller.
GWBF#
L5 I
Write Buffer Full.
SBA[7:0]
F3,E3,E1,D3,
D4, E4, C2, C3
I SideBand Address. Provides an additional bus to pass address and command
information from the master (graphics controller) to the target (VT8753 north
bridge logic). These pins are ignored until enabled.
SBS,
SBS#
D2,
D1
I Sideband Strobe. Driven by the master to provide timing for SBA[7:0]. SBS
is used for AGP 2x while SBS and SBS# are used together for AGP 4x.
ST[2:0]
J5, F5, E5 O Status (AGP only). Provides information from the arbiter to a master to
indicate what it may do. Only valid while GGNT# is asserted.
000 Indicates that previously requested low priority read or flush data is
being returned to the master (graphics controller).
001 Indicates that previously requested high priority read data is being
returned to the master.
010 Indicates that the master is to provide low priority write data for a
previously enqueued write command.
011 Indicates that the master is to provide high priority write data for a
previously enqueued write command.
100 Reserved. (arbiter must not issue, may be defined in the future).
101 Reserved. (arbiter must not issue, may be defined in the future).
110 Reserved. (arbiter must not issue, may be defined in the future).
111 Indicates that the master (graphics controller) has been given
permission to start a bus transaction. The master may enqueue AGP
requests by asserting PIPE# or start a PCI transaction by asserting
GFRM#. ST[2:0] are always outputs from the target (north bridge
logic) and inputs to the master (graphics controller).
GREQ#
C1 I Request. Master (graphics controller) request for use of the AGP bus.
GGNT#
B1 O Grant. Permission is given to the master (graphics controller) to use the AGP
bus.
Note: For PCI operation on the AGP bus, the following pins are not required:
- PERR# (parity and error reporting not required on transient data devices such as graphics controllers)
- LOCK# (no lock requirement on AGP)
- IDSEL (internally connected to AD16 on AGP-compliant masters)
Note: Separate system interrupts are not provided for AGP. The AGP connector provides interrupts via PCI bus INTA-B#.
Note: The AGP bus supports only one master directly (REQ[3:0]# and GNT[3:0]# are not provided). External logic is required to implement
additional master capability. Note that the arbitration mechanism on the AGP bus is different from the PCI bus.
Note: A separate reset is not required for the AGP bus (RESET# resets both PCI and AGP buses)
Note: Two mechanisms are provided by the AGP bus to enqueue master requests: GPIPE# (to send addresses multiplexed on the AD lines) and
the SBA port (to send addresses unmultiplexed). AGP masters implement one or the other or select one at initialization time (they are not
allowed to change during runtime). Therefore only one of the two will be used and the signals associated with the other will not be used.
Therefore the VT8753 has an internal pullup on GRBF# to maintain it in the de-asserted state in case it is not implemented on the master
device.