Product specifications

ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -13- Pin Descriptions
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Technologies, Inc.
AGP Bus Interface
Signal Name Pin # I/O Signal Description
GD[31:0]
(see
pin list)
IO Address / Data Bus. Address is driven with GDS assertion for AGP-style transfers and
with GFRM# assertion for PCI-style transfers.
GBE[3:0]#
K5,
M2,
N3,
R1
IO
Command / Byte Enables.
AGP: These pins provide command information (different commands than for PCI)
driven by the master (graphics controller) when requests are being enqueued using
GPIPE#. These pins provide valid byte information during AGP write transactions and
are driven by the master. The target (this chip) drives these lines to “0000” during the
return of AGP read data.
PCI: Commands are driven with GFRM# assertion. Byte enables corresponding to
supplied or requested data are driven on following clocks.
GPAR
U4 IO AGP Parity. A single parity bit is provided over GD[31:0] and GBE[3:0].
GDS0,
GDS0#
T4,
T5
IO Bus Strobe 0. Source synchronous strobes for GD[15:0] (the agent that is providing the
data drives these signals). GDS0 provides timing for 2x data transfer mode; GDS0 and
GDS0# provide timing for 4x transfer mode.
GDS1,
GDS1#
J3,
J2
IO Bus Strobe 1. Source synchronous strobes for GD[31:16] (i.e., the agent that is providing
the data drives these signals). GDS1 provides timing for 2x data transfer mode; GDS1
and GDS1# provide timing for 4x transfer mode.
GFRM#
L4 IO Frame. Assertion indicates the address phase of a PCI transfer. Negation indicates that
one more data transfer is desired by the cycle initiator.
GIRDY#
M1 IO
Initiator Ready.
AGP: For write operations, the assertion of this pin indicates that the master is ready to
provide all write data for the current transaction. Once this pin is asserted, the master is
not allowed to insert wait states. For read operations, the assertion of this pin indicates
that the master is ready to transfer a subsequent block of read data. The master is never
allowed to insert a wait state during the initial block of a read transaction. However, it
may insert wait states after each block transfers.
PCI: Asserted when the initiator is ready for data transfer.
GTRDY#
P5 IO
Target Ready.
AGP: Indicates that the target is ready to provide read data for the entire transaction
(when the transaction can complete within four clocks) or is ready to transfer a (initial or
subsequent) block of data when the transfer requires more than four clocks to complete.
The target is allowed to insert wait states after each block transfer for both read and write
transactions.
PCI: Asserted when the target is ready for data transfer.
GSTOP#
R5 IO Stop (PCI transactions only). Asserted by the target to request the master to stop the
current transaction.
GDEVSEL#
N4 IO Device Select (PCI transactions only). This signal is driven by the VT8753 when a PCI
initiator is attempting to access main memory. It is an input when the VT8753 is acting as
PCI initiator. Not used for AGP cycles.
GPIPE#
G5 I Pipelined Request. Asserted by the master (the external graphics controller) to indicate
that a full-width request is to be enqueued by the target VT8753. The master enqueues
one request each rising edge of GCLK while GPIPE# is asserted. When GPIPE# is
deasserted no new requests are enqueued across the AD bus.