Product specifications
ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -12- Pin Descriptions
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Technologies, Inc.
DRAM Interface
Signal Name Pin # I/O Signal Description
MD[63:0]
(see pin lists) IO Memory Data. These signals are connected to the
DRAM data bus. Output drive strength may be set by
Device 0 Rx6D[1-0].
MECC[7:0] / CKE[7:0] AE13, AJ13, AJ15, AH15,
AG13, AH14, AF14, AF15
IO DRAMECCorECData:when ECC is enabled.
Clock Enables: For each DRAM bank for powering
down the SDRAMs in notebook applications. Also used
in desktop systems for clock control to reduce power
usage and for reducing heat/temperature in high-speed
memory systems.
MAA[14:0]
AJ22, AE25, AG12, AJ7,
AH12, AF26, AG22,
AE22, AE20, AE21, AF17,
AG17, AJ17, AE16, AF12
O Memory Address A. DRAM address lines (two sets for
better drive). Output drive strength may be set by Device
0 Rx6C[7-6].
MAB[14:0]
AG21, AE26, AJ11, AH8,
AE11, AF27, AE23, AE24,
AG19, AF21, AJ18, AH17,
AJ16, AG15, AJ12
O Memory Address B. DRAM address lines (two sets for
better drive). Output drive strength may be set by Device
0 Rx6C[5-4].
SRASA#, SCASA#, SWEA# AG16, AE10, AE14 O
Row Address, Column Address and Write Enable
Command Indicator Set A. (two sets for better drive).
Output drive strength may be set by Device 0 Rx6C[7-6].
SRASB#, SCASB#, SWEB# AD19, AD16, AD17 O
Row Address, Column Address and Write Enable
Command Indicator Set B. (two sets for better drive).
Output drive strength may be set by Device 0 Rx6C[5-4].
CS[7:0]#
AE6, AE5, AF11, AE12,
AG7, AH6, AF8, AE9
O Chip Select. Chip select of each bank. Output drive
strength may be set by Device 0 Rx6D[3-2].
DQM[8],
DQM[7:0] /CKE[7:0]
AJ14,
AD4, AJ1, AH5, AJ9,
AJ20, AJ24, AH27, AE28
O Data Mask. Data mask of each byte lane plus DQM8
for ECC byte. Output drive strength may be set by
Device 0 Rx6D[5-4].
DQS[8],
DQS[7:0]# / CKE[7:0]
AG14,
AD3, AH1, AJ5, AH9,
AH20, AH24, AJ28, AE29
IO DDR Data Strobe. Data strobe of each byte lane plus
DQS8# for ECC byte. Output drive strength may be set
by Device 0 Rx6C[3-2].
CKE[7:0] / MECC[7:0]
-or-
CKE[7:0] /DQM[7:0]
-or-
CKE[7:0] /DQS[7:0]#
(see above) O Clock Enables. Clock enables for each DRAM bank for
powering down the SDRAM or clock control for
reducing power usage and for reducing heat / temperature
in high-speed memory systems. See Device 0 Rx78[0]
for CKE function enable.