Product specifications

ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -11- Pin Descriptions
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CPU Interface (continued)
Signal Name Pin # I/O Signal Description
BREQ#
L26 O Bus Request. Bus request output to CPU.
BPRI#
L29 IO Priority Agent Bus Request. The owner of this signal will always be the next bus owner.
This signal has priority over symmetric bus requests and causes the current symmetric
owner to stop issuing new transactions unless the HLOCK# signal is asserted. The P4M266
drives this signal to gain control of the processor bus.
BNR#
M29 IO Block Next Request. Used to block the current request bus owner from issuing new
requests. This signal is used to dynamically control the processor bus pipeline depth.
DEFER#
M27 IO Defer. The P4M266 uses a dynamic deferring policy to optimize system performance. The
P4M266 also uses the DEFER# signal to indicate a processor retry response.
CPURST#
E14 O CPU Reset. Reset output to CPU. External pullup and filter capacitor to ground should be
provided per CPU manufacturer’s recommendations.
The pinouts were defined assuming the ATX PCB layout model shown below (and general pin layout shown) as a guide for PCB
component placement. Other PCB layouts (AT, LPX, and NLX) were also considered and can typically follow the same general
component placement.
Figure 3. Reference Component Placement Using the P4M266 Chipset
DRAM Modules
IDE Connectors
PCI Slots
VT8233
South
Bridge
Power
Supply
CPU
AGP
A
…
F
126
VL
Pentium 4
CPU
CRT
/FPM
VT
8751
AGP
Slot
DRAM