Product specifications

ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -10- Pin Descriptions
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PIN DESCRIPTIONS
Table 4. VT8751 / P4M266 Pin Descriptions
CPU Interface
Signal Name Pin # I/O Signal Description
HA[33:3]#
(see pinout
tables)
IO Host CPU Address Bus. Connect to the address bus of the host CPU. Inputs during
CPU cycles and driven by the P4M266 during cache snooping operations. HA[33:32] are
reserved for future use in supporting up to 16 Gbytes of real memory.
HAS[1:0]#
Y27, T25 IO Host CPU Address Strobe. Source synchronous strobes used to transfer HA[31:3]# and
HREQ[4:0]# at a 2x transfer rate. HAS1# is the strobe for HA[31:17]# and HAS0# is the
strobe for HA[16:3] and HREQ[4:0]#.
HD[63:0]#
(see pinout
tables)
IO Host CPU Data. These signals are connected to the CPU data bus.
HDBI[3:0]#
D16, B22,
C25, G27
IO Host CPU Dynamic Bus Inversion. Driven along with HD[63:0]# to indicate if the
associated signals are inverted or not. Used to limit the number of simultaneously
switching signals to 8 for the associated 16-bit data pin group (HDBI3# for HD[63:48]#,
HDBI2# for HD[47:32]#, HDBI1# for HD[31:16]#, and HDBI0# for HD[15:0]#).
HDBIn# is asserted such that the number of data bits driven low for the corresponding
group does not exceed 8.
HDS[3:0]
HDS[3:0]#
C17, D20,
A27, G28
B17, E20,
B27, G29
IO Host CPU Differential Data Strobes. Source synchronous strobes used to transfer
HD[63:0]# and HDBI[3:0]# at a 4x transfer rate. HDS3 / HDS3# are the strobes for
HD[63:48]# and HDBI3#; HDS2 / HDS2# are the strobes for HD[47:32]# and HDBI2#;
HDS1 / HDS1# are the strobes for HD[31:16]# and HDBI1#; and HDS0 / HDS0# are the
strobes for HD[15:0]# and HDBI0#.
ADS#
P25 IO Address Strobe. The CPU asserts ADS# in T1 of the CPU bus cycle.
DBSY#
K25 IO Data Bus Busy. Used by the data bus owner to hold the data bus for transfers requiring
more than one cycle.
DRDY#
M28 IO Data Ready. Asserted for each cycle that data is transferred.
HIT#
L27 IO Hit. Indicates that a caching agent holds an unmodified version of the requested line.
Also driven in conjunction with HITM# by the target to extend the snoop window.
HITM#
J25 I Hit Modified. Asserted by the CPU to indicate that the address is modified in the L1
cache and needs to be written back.
HLOCK#
L25 I Host Lock. All CPU cycles sampled with the assertion of HLOCK# and ADS# until the
negation of HLOCK# must be atomic.
HREQ[4:0]#
P26, P29,
N27, P27,
R25
IO Request Command. Asserted during both clocks of the request phase. In the first clock,
the signals define the transaction type to a level of detail that is sufficient to begin a snoop
request. In the second clock, the signals carry additional information to define the
complete transaction type.
HTRDY#
M26 IO Host Target Ready. Indicates that the target of the processor transaction is able to enter
the data transfer phase.
RS[2:0]#
K27,
K29,
K28
IO Response Signals. Indicates the type of response per the table below:
RS[2:0]#
Response type RS[2:0]# Response type
000 Idle State 100 Hard Failure
001 Retry Response 101 Normal Without Data
010 Defer Response 110 Implicit Writeback
011 Reserved 111 Normal With Data
Note: Clocking of the CPU interface is performed with HCLK and HCLK#.
Note: Internal pullup resistors are provided on all AGTL+ interface pins. If the CPU does not have internal pullups, these north
bridge internal pullups may be enabled to allow the interface to meet AGTL+ bus interface specifications (see VAD3 strap).