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Single-Chip SMA North Bridge

for Pentium 4™ CPUs with 400 MHz FSB,

External 4x AGP Bus and

Integrated ProSavage8™ AGP Graphics Core

plus Advanced ECC Memory Controller

supporting PC2100 / PC1600 DDR SDRAM

and PC133 / PC100 SDR SDRAM

for Desktop PC Systems

Revision 1.1

July 19, 2002

a joint development of

VIA TECHNOLOGIES, INC.

and S3 GRAPHICS, INC.

Summary of content (68 pages)

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Single-Chip SMA North Bridge for Pentium 4™ CPUs with 400 MHz FSB, External 4x AGP Bus and Integrated ProSavage8™ AGP Graphics Core plus Advanced ECC Memory Controller supporting PC2100 / PC1600 DDR SDRAM and PC133 / PC100 SDR SDRAM for Desktop PC Systems Revision 1.1 July 19, 2002 a joint development of VIA TECHNOLOGIES, INC. and S3 GRAPHICS, INC.
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Copyright Notice: Copyright © 1999, 2000, 2001, 2002 VIA Technologies Incorporated. All Rights Reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise without the prior written permission of VIA Technologies Incorporated. The material in this document is for information only and is subject to change without notice.
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Technologies, Inc. ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge We Connect REVISION HISTORY Document Release 1.0 1.01 Date 2/13/02 3/19/02 1.1 7/19/02 Revision 1.1, July 19, 2002 Revision Initial external release (same as internal revision 0.
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge TABLE OF CONTENTS REVISION HISTORY .......................................................................................................................................................................I TABLE OF CONTENTS.................................................................................................................................................................. II LIST OF FIGURES .......................
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge PCI Configuration ................................................................................................................................................................ 53 PCI Subsystem ID................................................................................................................................................................. 54 Integrated AGP.................................................
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge LIST OF FIGURES FIGURE 1. P4M266 CHIPSET SYSTEM BLOCK DIAGRAM .................................................................................................. 4 FIGURE 2. VT8751 / P4M266 BALL DIAGRAM (TOP VIEW)................................................................................................. 7 FIGURE 3. REFERENCE COMPONENT PLACEMENT USING THE P4M266 CHIPSET ...............................................
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Technologies, Inc. We Connect • Integrated ProSavage8 2D / 3D Graphics Controller and Video Accelerator – – – – – – – – – – – – • Digital Visual Interface (DVI) 1.
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Technologies, Inc. ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge We Connect OVERVIEW The ProSavageDDR P4M266 (VT8751 North Bridge plus VT8233 South Bridge) is a high performance, cost-effective and energy efficient SMA chip set for the implementation of desktop personal computer systems with 400 MHz (100 MHz QDR) CPU host bus (“Front Side Bus”) based on 64-bit Intel Pentium-4 super-scalar processors.
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge P4M266 also integrates S3 Graphics’ 128-bit ProSavage8 graphics accelerator into a single chip. P4M266 brings mainstream graphics performance to the Value PC with leading-edge 2D, 3D and DVD video acceleration into a cost effective package. Based on its capabilities, P4M266 is an ideal solution for the consumer, corporate mobile users and entry level professionals.
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Technologies, Inc. ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge We Connect High Screen Resolution CRT Support Resolutions Supported 640x480x8/16/32 800x600x8/16/32 1024x768x8/16/32 1280x1024x8 1280x1024x16 1280x1024x32 1600x1200x8 1600x1200x16 1600x1200x32 1920x1440x8 1920x1440x16 System Memory Frame Buffer Size 8 MB 16/32 MB ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ Table 1. Supported CRT Screen Resolutions Revision 1.
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Technologies, Inc. ProSavageDDR P4M266 – VT8751 Pentium 4 DDR SMA North Bridge We Connect PINOUTS Key 1 A NC B G GNT# C G REQ# D SBS# E SBA 5 F GD31 Figure 2.
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Technologies, Inc. ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge We Connect Table 2.
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Technologies, Inc. ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge We Connect Table 3.
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Technologies, Inc. ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge We Connect PIN DESCRIPTIONS Table 4. VT8751 / P4M266 Pin Descriptions CPU Interface Signal Name Pin # I/O Signal Description HA[33:3]# (see pinout tables) IO HAS[1:0]# Y27, T25 IO HD[63:0]# (see pinout tables) D16, B22, C25, G27 IO Host CPU Address Bus. Connect to the address bus of the host CPU. Inputs during CPU cycles and driven by the P4M266 during cache snooping operations.
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Technologies, Inc. ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge We Connect CPU Interface (continued) Signal Name Pin # I/O Signal Description BREQ# BPRI# L26 L29 O IO BNR# M29 IO DEFER# M27 IO CPURST# E14 O Bus Request. Bus request output to CPU. Priority Agent Bus Request. The owner of this signal will always be the next bus owner.
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge DRAM Interface Signal Name Pin # I/O Signal Description (see pin lists) IO MECC[7:0] / CKE[7:0] AE13, AJ13, AJ15, AH15, AG13, AH14, AF14, AF15 IO MAA[14:0] O O Memory Address B. DRAM address lines (two sets for better drive). Output drive strength may be set by Device 0 Rx6C[5-4].
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Technologies, Inc. ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge We Connect AGP Bus Interface Signal Name Pin # I/O Signal Description GD[31:0] (see pinlist) K5, M2, N3, R1 IO GPAR GDS0, GDS0# U4 T4, T5 IO IO GDS1, GDS1# J3, J2 IO GFRM# L4 IO GIRDY# M1 IO GTRDY# P5 IO GSTOP# R5 IO GDEVSEL# N4 IO GPIPE# G5 I Address / Data Bus. Address is driven with GDS assertion for AGP-style transfers and with GFRM# assertion for PCI-style transfers. Command / Byte Enables.
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Technologies, Inc. ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge We Connect AGP Bus Interface (continued) Signal Name Pin # I/O H5 I L5 F3, E3, E1, D3, D4, E4, C2, C3 I I SBS, SBS# ST[2:0] D2, D1 J5, F5, E5 I O GREQ# GGNT# C1 B1 I O GRBF# GWBF# SBA[7:0] Signal Description Read Buffer Full. Indicates if the master (graphics controller) is ready to accept previously requested low priority read data.
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Technologies, Inc. ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge We Connect V-Link Interface Signal Name Pin # I/O Signal Description VAD7, VAD6 / strap, VAD5 / strap, VAD4 / strap, VAD3 / strap, VAD2 / strap, VAD1 / strap, VAD0 / strap AB2 AB1 W2 AA5 W1 AB3 W3 W5 IO IO IO IO IO IO IO IO Address / Data Bus.
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Technologies, Inc. ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge We Connect Clocks, Resets, Power Control, General Purpose I/O, Interrupts and Test Signal Name Pin # I/O HCLK N25 I HCLK# MCLK M25 AC25 I O MCLKF DCLKI AD25 C8 I I DCLKO D8 O GCLK XIN / XDCLK U5 A7 I I RESET# AC3 I PWROK SUSST# AC1 AC4 I I GPOUT GOP0 / XECLK D11 E10 O O INTA# BISTIN# A9 B9 O I TESTIN# W25 I A7 E10 A1, F2, M5, AD8, AE8 I I – XDCLK / XIN XECLK / GOP0 NC Revision 1.
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Technologies, Inc. ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge We Connect Configuration Straps Signal Name Pin # I/O Strap / FPD9 / TVD9, Strap / FPD7 / TVD7, Strap / FPD6 / TVD6, Strap / FPD5 / TVD5, Strap / FPD4 / TVD4, Strap / FPD3 / TVD3, Strap / FPD2 / TVD2, Strap / FPD1 / TVD1, Strap / FPD0 / TVD0 E12 A12 C12 D12 E13 D13 A13 B13 C13 I Signal Description Straps.
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Technologies, Inc. ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge We Connect Analog Power / Ground Signal Name Pin # I/O VCCHCK GNDHCK N24 M24 P P VCCMCK GNDMCK VCCMDLL GNDMDLL AD24 AC24 AE15 AD15 P P P P VCCRGB GNDRGB VCCDAC GNDDAC VCCPLL1 GNDPLL1 VCCPLL2 GNDPLL2 E6 C5 C6 D6 C7 B7 E7 D7 P P P P P P P P Signal Description Power for Host CPU Clock PLL (2.5V ±5%) Ground for Host CPU Clock Circuitry. Connect to main ground plane through a ferrite bead. Power for Memory Clock PLL (2.
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge REGISTERS Register Overview The following tables summarize the configuration and I/O registers of the P4M266. These tables also document the power-on default value (“Default”) and access type (“Acc”) for each register.
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Technologies, Inc. ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge We Connect Device 0 Device-Specific Registers (continued) Device 0 Device-Specific Registers (continued) Offset 83-80 84 85 86-87 8B-88 8C-9F GART/TLB Control Default Acc GART/TLB Control 0000 0000 RW Graphics Aperture Size 00 RW Write Policy 00 RW -reserved00 — Gr.
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge Miscellaneous I/O Configuration Space I/O One I/O port is defined in the P4M266: Port 22. All registers in the P4M266 (listed above) are addressed via the following configuration mechanism: Port 22 – PCI / AGP Arbiter Disable ..............................RW 7-2 Reserved ........................................ always reads 0 1 AGP Arbiter Disable 0 Respond to GREQ# signal .....................
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge Device 0 Register Descriptions Device 0 Offset 7-6 – Status (0210h)..............................RWC 15 Detected Parity Error 0 No parity error detected......................... default 1 Error detected in either address or data phase. This bit is set even if error response is disabled (command register bit-6). ....write one to clear 14 Signaled System Error (SERR# Asserted) ........................................
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge Device 0 Host Bridge Header Registers (continued) Device 0 Offset 2D-2C – Subsystem Vendor ID (0000h)R/W1 15-0 Subsystem Vendor ID .............................. default = 0 This register may be written once and is then read only. Device 0 Offset E - Header Type (00h).............................RO 7-0 Header Type Code ............. reads 00: single function Device 0 Offset F - Built In Self Test (BIST) (00h)..........
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge Device 0 Host Bridge Device-Specific Registers These registers are normally programmed once at system initialization time. V-Link Control Device 0 Offset 40 – V-Link Specification ID (00h) ........RO 7-0 Specification Revision...................... always reads 00 Device 0 Offset 45 –NB V-Link Bus Timer (44h)...........
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge Device 0 Offset 48 – NB/SB V-Link Configuration (18h)RW 7 Reserved ........................................always reads 0 6 Rest Bus Width Supported 0 Not Supported ....................................... default 1 Supported 5 16-bit Bus Width Supported 0 Not Supported ....................................... default 1 Supported 4 8-Bit Bus Width Supported 0 Not Supported 1 Supported .........................................
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge Device 0 Offset 4E – CCA Master Priority (00h)........... RW 7 1394 High Priority 0 Low priority........................................... default 1 High priority 6 LAN / NIC High Priority 0 Low priority........................................... default 1 High priority 5 Reserved ........................................always reads 0 4 USB High Priority 0 Low priority...........................................
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge Host CPU Control Device 0 Offset 51 – CPU Interface Basic Control (00h)RW 7 CPU Read DRAM Fast Ready 0 Medium / Slow Ready (see bit 0) .......... default 1 Fast Ready (bit-0 of this register is ignored) 6 Read Around Write 0 Disable................................................... default 1 Enable 5 DRQ Control 0 Non pipelined similar to VT8633.......... default 1 Pipelined 4 CPU to PCI Read Defer 0 Disable..............
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge Device 0 Offset 52 – CPU Interface Advanced Ctrl (00h)RW 7 CPU RW DRAM 0WS for Back-to-Back Pipeline Access 0 Disable ...................................................default 1 Enable 6 HREQ High Priority 0 Disable ...................................................default 1 Enable 5 C2P2 Timing 0 Compatible.............................................default 1 Enhanced This bit should always be set to 1.
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Technologies, Inc. ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge We Connect DRAM Control These registers are normally set at system initialization time and not accessed after that during normal system operation. Some of these registers, however, may need to be programmed using specific sequences during power-up initialization to properly detect the type and size of installed memory (refer to the VIA Technologies VT8751 BIOS porting guide for details). Device 0 Offset 55 – DRAM Control (00h)......
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge Device 0 Offset 5F-5A – DRAM Row Ending Address: Offset 5A – Bank 0 Ending (HA[31:24]) (01h) .......... RW Offset 5B – Bank 1 Ending (HA[31:24]) (01h) .......... RW Offset 5C – Bank 2 Ending (HA[31:24]) (01h) .......... RW Offset 5D – Bank 3 Ending (HA[31:24]) (01h) .......... RW Offset 5E – Bank 4 Ending (HA[31:24]) (01h) .......... RW Offset 5F – Bank 5 Ending (HA[31:24]) (01h) ..........
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge Device 0 Offset 63 - Shadow RAM Control 3 (00h) ....... RW 7-6 E0000h-EFFFFh 00 Read/write disable ................................. default 01 Write enable 10 Read enable 11 Read/write enable 5-4 F0000h-FFFFFh 00 Read/write disable ................................. default 01 Write enable 10 Read enable 11 Read/write enable 3-2 Memory Hole 00 None ....................................................
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge Device 0 Offset 64 - DRAM Timing for All Banks (E4h)RW 7 Precharge Command to Active Command Period 0 TRP = 2T 1 TRP = 3T................................................default 6 Active Command to Precharge Command Period 0 TRAS = 5T 1 TRAS = 6T..............................................default 5-4 CAS Latency SDR DDR 00 1T 01 2T 2T 10 3T 2.5T...........................................default 11 3T 3 Reserved ..........
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge Device 0 Offset 6A - Refresh Counter (00h)................... RW 7-0 Refresh Counter (in units of 16 MCLKs) 00 DRAM Refresh Disabled ...................... default 01 32 MCLKs 02 48 MCLKs 03 64 MCLKs 04 80 MCLKs 05 96 MCLKs … … Device 0 Offset 69 – DRAM Clock Select (00h)..............RW 7 CPU Operating Frequency Faster Than DRAM 0 CPU Same As or Equal to DRAM.........
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge Device 0 Offset 6D – DRAM Drive Control 2 (00h)....... RW 7-6 Early Clock Select for SCMD, MA Output (for 1T Command) 00 Latest .................................................... default 01 10 11 Earliest 5-4 DQM Drive 00 Lowest ................................................... default 01 10 11 Highest 3-2 CS# Drive 00 Lowest ...................................................
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Technologies, Inc. ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge We Connect If error checking / reporting only (EC) is selected, all read and write cycles will use normal timing. Partial writes (with EC or ECC enabled) will use read-modify-write cycles to maintain correct error correction codes in the additional 8 data bits.
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge PCI Bus Control These registers are normally programmed once at system initialization time. Device 0 Offset 73 - PCI Master Control (00h) .............. RW 7 Reserved ........................................always reads 0 6 PCI Master 1-Wait-State Write 0 Zero wait state TRDY# response........... default 1 One wait state TRDY# response 5 PCI Master 1-Wait-State Read 0 Zero wait state TRDY# response...........
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge Device 0 Offset 76 - PCI Arbitration 2 (00h).................. RW 7 I/O Port 22 Access 0 CPU access to I/O address 22h is passed on to the PCI bus ............................................ default 1 CPU access to I/O address 22h is processed internally 6 Reserved ........................................always reads 0 5-4 Master Priority Rotation Control 00 Disable...................................................
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Technologies, Inc. ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge We Connect Device 0 Offset 83-80 - GART/TLB Control (00000000h) RW 31-16 Reserved ........................................always reads 0 15-8 Reserved (test mode status) .................................RO 7 Flush Page TLB 0 Disable................................................... default 1 Enable 6-0 Reserved ........................................
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge AGP Control Device 0 Offset AC - AGP Control (00h)........................ RW 7 AGP Disable..........................................................RO 0 Disable................................................... default 1 Enable This bit is latched from MA9 at the rising edge of RESET#. 6 AGP Read Synchronization 0 Disable...................................................
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge AGP Control (continued) Device 0 Offset AD – AGP Miscellaneous Control (02h)RW 7 AGP Performance Improvement 0 Disable ...................................................default 1 Enable 6 Pipe Mode Performance Improvement 0 Disable ...................................................default 1 Enable 5 Input on AGP GD / GBE Pads 0 Disable ...................................................
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge V-Link Control Device 0 Offset B4 – V-Link NB Compensation Ctrl (00h)RW 7-6 V-Link Autocomp Output Value...... always reads 0 5 Pullup Compensation Selection 0 Auto Comp (use values in bits 7-6)........default 1 Manual Comp (use values in bits 3-2) 4 Pulldown Compensation Selection 0 Auto Comp (use values in bits 7-6)........default 1 Manual Comp (use values in bits 1-0) 3-2 Pullup Compensation Manual Setting .........
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge DRAM Interface Control Power Management Device 0 Offset BE – MECC Drive Strength (00h) ........RW 7-6 MECC Drive Strength ............................ default = 0 5-0 Reserved ........................................ always reads 0 Device 0 Offset C0 – Power Management Capability IDRO 7-0 Capability ID ..................................
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge AGTL+ I/O Control Device 0 Offset DD – AGTL+ I/O Control (00h) ........... RW 7 AGTL+ 4x Input Increase Delay to Filter Noise 0 Disable................................................... default 1 Enable 6 AGTL+ 2x Input Increase Delay to Filter Noise 0 Disable................................................... default 1 Enable 5 AGTL+ Slew Rate Control 0 Disable...................................................
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge Frame Buffer and High Memory Control Device 0 Offset E4 – Low Top Address Low (00h) ........ RW 7-4 Low Top Address Low............................. default = 0 3-0 DRAM Granularity 0 16M Total DRAM less than 4G ........
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge Device 1 Register Descriptions Device 1 Offset 7-6 - Status (Primary Bus) (0230h).....RWC 15 Detected Parity Error ........................always reads 0 14 Signaled System Error (SERR#).......always reads 0 13 Signaled Master Abort 0 No abort received .................................. default 1 Transaction aborted by the master with Master-Abort (except Special Cycles).............. ......................................
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge Device 1 Offset 3F-3E – PCI-to-PCI Bridge Control (0000h) .............................................................................. RW 15-4 Reserved ........................................always reads 0 3 VGA-Present on AGP 0 Forward VGA accesses to PCI Bus....... default 1 Forward VGA accesses to AGP Bus Note: VGA addresses are memory A0000-BFFFFh and I/O addresses 3B0-3BBh, 3C0-3CFh and 3D03DFh (10-bit decode).
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Technologies, Inc. ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge We Connect Device 1 PCI-to-PCI Bridge Device-Specific Registers AGP Bus Control Device 1 Offset 40 - CPU-to-AGP Flow Control 1 (00h) RW 7 CPU-AGP Post Write 0 Disable ...................................................default 1 Enable 6 Reserved ........................................ always reads 0 5 CPU-AGP One Wait State Burst Write 0 Disable ...................................................
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge Device 1 Offset 45 – Fast Write Control (72h) ............... RW 7 Force Fast Write Cycle to be QW Aligned (if Rx45[6] = 0) 0 Disable................................................... default 1 Enable 6 Merge Multiple CPU Transactions Into One Fast Write Burst Transaction 0 Disable 1 Enable...................................................
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge Device 1 Offset 80 – Capability ID (01h)..........................RO 7-0 Capability ID.................................. always reads 01h Device 1 Offset 84 – Power Mgmt Ctrl/Status (00h)...... RW 7-2 Reserved ........................................always reads 0 1-0 Power State 00 D0 .................................................... default 01 -reserved10 -reserved11 D3 Hot Device 1 Offset 81 – Next Pointer (00h)...
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Technologies, Inc. ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge We Connect FUNCTIONAL DESCRIPTION - INTEGRATED SAVAGE4 GRAPHICS Configuration Strapping PCI Configuration and Integrated AGP Certain P4M266 graphics functions have options that must be selected and fixed at reset (before the register bits controlling these functions can be programmed by software). This is accomplished via power-on configuration strapping.
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Technologies, Inc. ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge We Connect PCI Subsystem ID Integrated AGP The Subsystem ID and Subsystem Vendor ID are located in a 32-bit read only register at PCI Configuration Space Index 2C. These registers reflect the content of 4 read/write CR registers as follows: P4M266 graphics conform with the requirements of Revision 2.0 of the AGP Interface Specification.
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Technologies, Inc. We Connect ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge Display Memory Interrupt Generation The P4M266 north bridge utilizes a Shared Memory Architecture (SMA) for Frame Buffer Memory. SMA allows system memory to be efficiently shared by the host CPU and the P4M266 north bridge graphics controller.
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Technologies, Inc. ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge We Connect Display Interfaces TFT Flat Panel DVI Interface CRT Interface Figure 5 shows the hardware connections to a transceiver conforming to the DVI 1.0 standard. This interface allows the P4N266 to drive a TFT flat panel over considerable distance and is active when CRB0[3] = 1 and CRB0[4] = 1. Panel power sequencing is controlled by the receiver components.
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Technologies, Inc. ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge We Connect External TV Encoder Interface I2C Serial Communications Port Figure 6 shows the interface to an external TV encoder (BT868/869, VIA VT1621, or compatible device). The TV outputs are generated whenever the clock input from the decoder is present on the TVCLK pin, CRB0[3] = 1, and CRB0[4] = 0. The encoder is controlled via the I2C interface. TV monitor detection is also done via this interface.
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Technologies, Inc. ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge We Connect ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Table 15. Absolute Maximum Ratings Symbol TC Parameter Min Case operating temperature Max Unit Notes 85 oC 1 1 0 TS Storage temperature -55 125 oC VIN Input voltage -0.5 VRAIL + 10% Volts 1, 2 Output voltage -0.5 VRAIL + 10% Volts 1, 2 VOUT Note 1. Stress above the conditions listed may cause permanent damage to the device.
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Technologies, Inc. ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge We Connect Power Characteristics TC = 0-85oC, VRAIL = VCC +/- 5%, VCORE = 2.5V +/- 5%, GND=0V Table 18. Power Characteristics – Internal and Interface Digital Logic Symbol Parameter Typ Max Unit Condition ITT Power Supply Current – VTT 46 mA Full-On Operation ITTPOS Power Supply Current – VTT 54.5 mA POS ITTSTR Power Supply Current – VTT 0.002 mA STR ITTSOF Power Supply Current – VTT 0.
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Technologies, Inc. ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge We Connect Table 19.
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Technologies, Inc. ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge We Connect Table 21. AC Timing – CPU Interface Signal Reference Signal Setup Hold Min Delay Max Delay Unit HD Bus HDS[3:0]# 0.55 0.55 0.85 0.80 ns HA Bus HAS[1:0]# 0.50 0.55 1.6 1.6 ns HREQ[4:0]# HAS0# 0.50 0.55 1.6 1.6 ns ADS# HCLK 2.4 –0.20 ns DBSY# HCLK 2.4 –0.20 ns DRDY# HCLK 2.4 –0.20 ns HIT# HCLK 2.4 –0.20 ns HITM# HCLK 2.4 –0.20 ns HLOCK# HCLK 2.4 –0.20 ns Table 22.
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Technologies, Inc. ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge We Connect MECHANICAL SPECIFICATIONS 34.50 REF Ø 1.00(3X) REF 4.60*45º (4X) 29 28 27 26 25 24 23 22 Chipset Name 21 20 19 34.