Product specifications

CN333 Data Sheet
Revision 1.0, January 5, 2005 -69- Device 1 Register Descriptions - PCI-to-PCI Bridge
Device 1 Device-Specific Registers
AGP Bus Control
Device 1 Offset 40 - CPU-to-AGP Flow Control 1 (00h)RW
7 CPU-AGP Post Write
0 Disable ...................................................default
1 Enable
6 CPU-AGP One Wait State Burst Write
0 Disable ...................................................default
1 Enable
5-4 Read Prefetch Control
00 Always prefetch .....................................default
x1 Never prefetch
10 Prefetch only for Enhance command
3 Reserved ........................................ always reads 0
2 MDA Present on AGP
0 Forward MDA accesses to AGP ............default
1 Forward MDA accesses to PCI
Note: Forward despite IO / Memory Base / Limit
Note: MDA (Monochrome Display Adapter)
addresses are memory addresses B0000h-B7FFFh
and I/O addresses 3B4-3B5h, 3B8-3BAh and 3BFh
(10-bit decode). 3BC-3BE are reserved for printers.
Note: If Rx3E bit-3 is 0, this bit is a don't care (MDA
accesses are forwarded to the PCI bus).
1 AGP Master Read Caching
0 Disable ...................................................default
1 Enable
0 AGP Delay Transaction
0 Disable ...................................................default
1 Enable
Table 10. VGA/MDA Memory/IO Redirection
3E[3]
VGA
Pres.
40[2]
MDA
Pres.
VGA
is
on
MDA
is
on
Axxxx,
B8xxx
Access
B0000
-B7FFF
Access
3Cx,
3Dx
I/O
3Bx
I/O
0 - PCI PCI PCI PCI PCI PCI
1 0 AGP AGP AGP AGP AGP AGP
1 1 AGP PCI AGP PCI AGP PCI
Device 1 Offset 41 - CPU-to-AGP Flow Control 2 (08h) RW
7 Retry Status
0 No retry occurred................................... default
1 Retry Occurred ........................write 1 to clear
6 Retry Timeout Action
0 No action taken except to record status ....... def
1 Flush buffer for write or return all 1s for read
5-4 Retry Count
00 Retry 2, backoff CPU ............................ default
01 Retry 4, backoff CPU
10 Retry 16, backoff CPU
11 Retry 64, backoff CPU
3 CPU-to-AGP Bursting Timeout
0 Disable
1 Enable................................................... default
2 Reserved ........................................always reads 0
1 CPU-to-PCI/AGP Cycles Invalidate PCI/AGP
Buffered Read Data
0 Disable................................................... default
1 Enable
0 Reserved ........................................always reads 0
Device 1 Offset 42 - AGP Master Control (00h) ............ RW
7 Reserved (Must Be Programmed to 1) .........def = 0
When this bit is set, the North Bridge will
automatically resolve the problem of AGP master
cycles being blocked by PCI Master Cycles.
6 AGP Master One Wait State Write
0 Disable................................................... default
1 Enable
5 AGP Master One Wait State Read
0 Disable................................................... default
1 Enable
4 Break Consecutive PCI Master Accesses
0 Disable................................................... default
1 Enable
3 Reserved ........................................always reads 0
2 Claim I/O R/W and Memory Read Cycles
0 Disable................................................... default
1 Enable
1 Claim Local APIC FEEx xxxx Cycles
0 Disable................................................... default
1 Enable
0 Snoop Write Enable 2T Rate, Support Host Side
Snoop Cycles at 2T Rate
0 Disable................................................... default
1 Enable