Product specifications

CN333 Data Sheet
Revision 1.0, January 5, 2005 -68- Device 1 Register Descriptions - PCI-to-PCI Bridge
Device 1 Offset 13-10 – Graphics Aperture Base (0000
0008h).................................................................................RW
This register is interpreted per the following definition if
RxFD[1]=1 (AGP 2.0 registers enabled).
31-22 Programmable Base Address Bits .................. def=0
These bits behave as if hardwired to 0 if the
corresponding AGP 3.0 Graphics Aperture Size
register bit (Device 0 Function 0 Offset 94h) is 0.
31 30 29 28 - - 27 26 25 24 23 22 (Base)
11
10 9 8 7 6 5 4 3 2 1 0 (Size)
RW RW RW RW 0 0 RW RW RW RW RW RW 4M
RW RW RW RW 0 0 RW RW RW RW RW 0 8M
RW RW RW RW 0 0 RW RW RW RW 0 0 16M
RW RW RW RW 0 0 RW RW RW 0 0 0 32M
RW RW RW RW 0 0 RW RW 0 0 0 0 64M
RW RW RW RW 0 0 RW 0 0 0 0 0 128M
RW RW RW RW 0 0 0 0 0 0 0 0 256M
RW RW RW 0 0 0 0 0 0 0 0 0 512M
RW RW 0 0 0 0 0 0 0 0 0 0 1G
RW 0 0 0 0 0 0 0 0 0 0 0 2G-max
0 0 0 0 0 0 0 0 0 0 0 0 4G
21-4 Reserved ........................................ always reads 0
3 Prefetchable.......................................always reads 1
2-1 Type ........................................ always reads 0
0 Memory Space.................................... always reads 0
Device 1 Offset 18 - Primary Bus Number (00h)............RW
7-0 Primary Bus Number .............................. default = 0
This register is read write, but internally the chip always uses
bus 0 as the primary.
Device 1 Offset 19 - Secondary Bus Number (00h) ........RW
7-0 Secondary Bus Number........................... default = 0
Note: AGP must use these bits to convert Type 1 to Type 0.
Device 1 Offset 1A - Subordinate Bus Number (00h) ....RW
7-0 Primary Bus Number .............................. default = 0
Note: AGP must use these bits to decide if Type 1 to Type 1
command passing is allowed.
Device 1 Offset 1C - I/O Base (F0h).................................RW
7-4 I/O Base AD[15:12].......................... default = 1111b
3-0 I/O Addressing Capability ...................... default = 0
Device 1 Offset 1D - I/O Limit (00h)................................RW
7-4 I/O Limit AD[15:12] ................................ default = 0
3-0 I/O Addressing Capability ...................... default = 0
Device 1 Offset 1F-1E - Secondary Status ....................... RO
15-0 Secondary Status
Rx44[4] = 0: these bits read back 0000h
Rx44[4] = 1: these bits read back same as Rx7-6
Device 1 Offset 21-20 - Memory Base (FFF0h) .............. RW
15-4 Memory Base AD[31:20] .................. default = FFFh
3-0 Reserved ........................................always reads 0
Device 1 Offset 23-22 - Memory Limit (Inclusive) (0000h) RW
15-4 Memory Limit AD[31:20]........................default = 0
3-0 Reserved ........................................always reads 0
Device 1 Offset 25-24 - Prefetchable Mem Base (FFF0h) RW
15-4 Prefetchable Memory Base AD[31:20]default = FFFh
3-0 Reserved ........................................always reads 0
Device 1 Offset 27-26 - Prefetchable Memory Limit
(0000h) .............................................................................. RW
15-4 Prefetchable Memory Limit AD[31:20]..default = 0
3-0 Reserved ........................................always reads 0
Device 1 Offset 34 - Capability Pointer (70h).................. RO
Contains an offset from the start of configuration space.
7-0 AGP Capability List Pointer .........always reads 70h