Product specifications

CN333 Data Sheet
Revision 1.0, January 5, 2005 -1- Product Features
CN333 NORTH BRIDGE
133 / 100 MHz VIA C3 Front Side Bus
Integrated UniChrome Pro 3D / 2D Graphics and Video Controllers
Advanced DDR333 SDRAM Controller
1 GB / Sec Ultra V-Link Interface
PRODUCT FEATURES
• Defines Highly Integrated Solutions for Full Featured, Power Efficient PC Designs
– High Performance UMA North Bridge: Integrated VIA C3 North Bridge with 133 / 100 MHz FSB support and
UniChrome Pro 3D / 2D Graphics and Video Controllers in a single chip
– Advanced memory controller supporting DDR 333 / 266 / 200 SDRAM
– Combines with VIA VT8235M-CE / VT8237R South Bridge for integrated 10/100 LAN, Audio, ATA133 IDE, LPC,
USB 2.0 and Serial ATA (VT8237R)
– “Lead-Free” 31 x 31mm HSBGA (Ball Grid Array with Heat Spreader) package with 681 balls and 1mm ball pitch
• High Performance CPU Interface
– Supports 133 / 100 MHz FSB VIA C3 processors
– Eight outstanding transactions (eight-level In-Order Queue (IOQ))
– Built-in Phase Lock Loop circuitry for optimal skew control within and between clocking regions
• Advanced High-Performance 64-Bit DDR SDRAM Controller
– Supports DDR333 / 266 memory types with 2.5V SSTL-2 DRAM interface
– Supports mixed 64 / 128 / 256 / 512 / 1024Mb DDR SDRAMs in x8 and x16 configurations
– Supports CL 2 / 2.5 for DDR266 / 333
– Supports 2 unbuffered double-sided DIMMs and up to 4 GBytes of physical memory
– Programmable timing / drive for memory address, data and control signals
– DRAM interface pseudo-synchronous with host CPU for optimal memory performance
– Concurrent CPU, internal graphics controller and V-Link access for minimum memory access latency
– Rank interleave and up to 16-bank page interleave (i.e., 16 pages open simultaneously) based on LRU to effectively
reduce memory access latency
– Seamless DRAM command scheduling for maximum DRAM bus utilization
– (e.g., precharge other banks while accessing the current bank)
– CPU Read-Around-Write capability for non-stalled operation
– Speculative DRAM read before snoop result to reduce PCI master memory read latency
– Supports Burst Read and Write operations with burst length of 4 or 8
– Eight cache lines (64 quadwords) of integrated CPU-to-DRAM write buffers and eight separate cache lines of CPU-
to-DRAM read prefetch buffers
– Optional dynamic Clock Enable (CKE) control for DRAM power reduction during normal system state (S0)
– Supports self-refresh and CAS-before-RAS DRAM refresh with staggered RAS timing
• High Bandwidth 1 GB / Sec 16-Bit “Ultra V-Link” Host Controller
– Supports 66 MHz, 4x and 8x transfer modes, Ultra V-Link Host interface with 1 GB / Sec total bandwidth
– Full duplex transfers with separate command / strobe for 4x and 8x modes
– Request / Data split transaction
– Transaction assurance for V-Link Host-to-Client access eliminates V-Link Host-Client Retry cycles
– Intelligent V-Link transaction protocol to minimize data wait-states, throttle transfer latency and avoid data overflow
– Highly efficient V-Link arbitration with minimum overhead