Product specifications

CN333 Data Sheet
Revision 1.0, January 5, 2005 -54- Device 0 Function 3 Register Descriptions - DRAM
UMA Control
Offset A0 – CPU Direct Access FB Base Address (00h).RW
7-1 CPU Direct Access FB Address [27:21] ....... def = 0
0 CPU Direct Access FB
0 Disable ...................................................default
1 Enable
Offset A1 – CPU Direct Access FB Size (00h).................RW
7 VGA
0 Disable ...................................................default
1 Enable
6-4 CPU Direct Access FB Size
000 None .....................................................default
001 2MB†
010 4MB†
011 8MB†
100 16MB
101 32 MB
110 64 MB
111 -reserved-
†Microsoft WHQL DCT certification requires the
frame buffer size to be a minimum of 16MB.
Smaller frame buffer sizes are supported for non-
Windows applications to reserve more available
memory for the system.
3-0 CPU Direct Access FB Address [31:28] ....... def = 0
Offset A2 – VGA Timer 1 (00h) .......................................RW
7-4 VGA High Priority Timer............................. def = 0
3-0 VGA Timer .................................................... def = 0
(programmed in units of 16 dot clocks)
Offset A3 – VGA Timer 2 (00h) .......................................RW
7-4 Timer to Promote Graphics Priority............ def = 0
(programmed in units of 16 dot clocks)
3-2 Reserved ........................................ always reads 0
1-0 Reserved (Do Not Program).................... default = 0
Offset A4 – Graphics Miscellaneous Control (00h) ....... RW
7-4 Reserved ........................................always reads 0
3 AGP DIO (Pad) Clock
0 Disable................................................... default
1 Enable
2 Graphics Data Delay to Sync with Clock
0 No sync.................................................. default
1 Sync with clock
1-0 Graphics DISPCLK Delay Control
00 .................................................... default
01
10
11