Product specifications

CN333 Data Sheet
Revision 1.0, January 5, 2005 -49- Device 0 Function 3 Register Descriptions - DRAM
Offset 70 – DRAM DDR Control 1 (00h) ........................RW
7-0 Channel A DQS Output Delay
00h .....................................................default
FFh
Offset 71 – DRAM DDR Control 2 (00h) ........................RW
7-0 Channel A MD Output Delay
00h .....................................................default
FFh
Offset 72 – DRAM DDR Control 3 (00h) ........................RW
7-0 Channel B DQS Output Delay
00h .....................................................default
FFh
Offset 73 – DRAM DDR Control 4 (00h) ........................RW
7-0 Channel B MD Output Delay
00h .....................................................default
FFh
Offset 74 – DRAM DQS Input Delay (00h).....................RW
7 DQS Input Delay Setting
0 Auto .....................................................default
1 Manual
6 Reserved ........................................ always reads 0
5-0 DQS Input Delay
(if bit-7 = 0, reads DLL calibration result)
00h .....................................................default
FFh
Offset 76 – DRAM Early Clock Select (00h)...................RW
7 Early Clock Select - Scmd/MA Bit-2 (see bits 3-2)
6 Early Clock Select - CS, CKE Bit-2 (see bits 1-0)
5-4 Reserved (Do Not Program).................... default = 0
3-2 Early Clock Select - Scmd/MA Bits 1-0 (see bit-7)
000 .....................................................default
001
010
011
100
101
110
111
1-0 Early Clock Select - CS, CKE Bits 1-0 (see bit-6)
000 .....................................................default
001
010
011
100
101
110
111
Offset 78 – DRAM Timing Control (13h)....................... RW
7-6 Reserved (Do Not Program)....................default = 0
5-4 Write MD / DQS / CAS Timing Range Control
00
01 ................................................... default
10
11
3-0 Reserved (Do Not Program) ................... default = 3
Offset 79 – DRAM DQS Output Control (01h).............. RW
7-4 Reserved ........................................always reads 0
3 DQS / MD Output Enable Gated with DQS Input
Enable
0 Disable................................................... default
1 Enable
2 DQS Output Long Postamble
0 Disable................................................... default
1 Enable
1 DQS Output Long Preamble 2
0 Disable................................................... default
1 Enable
0 DQS Output Long Preamble
0 Disable
1 Enable................................................... default