Product specifications

CN333 Data Sheet
Revision 1.0, January 5, 2005 -48- Device 0 Function 3 Register Descriptions - DRAM
Offset 6C – DRAM Clock Control (00h).........................RW
7-5 Reserved ........................................ always reads 0
4 DQM Removal (Always Perform 4-Burst R/W)
0 Disable ...................................................default
1 Enable
3 Reserved (Do Not Program).................... default = 0
2 DDR x4 Device Enable
0 Disable ...................................................default
1 Enable
1-0 Reserved (Do Not Program).................... default = 0
Offset 6E – DRAM Control (00h) ................................... RW
7 Reserved ........................................always reads 0
6 DRAM Scrubber
0 Disable................................................... default
1 Enable
5 DRAM Scrubber Redirect
0 Disable................................................... default
1 Enable
4-3 Reserved ........................................always reads 0
2 For Double-Sided DIMMs, Interleave Using
Address Bit-15
0 Disable................................................... default
1 Enable
1 Select Address Bit 19 Instead of 14 as Sub-Bank
Address
0 Disable................................................... default
1 Enable
0 Select Address Bit 18 Instead of 13 as Sub-Bank
Address
0 Disable................................................... default
1 Enable
Note: Refer to the CN333 BIOS Porting Guide for SDRAM
configuration algorithms and recommended settings for these
bits for typical memory system configurations.