Product specifications

CN333 Data Sheet
Revision 1.0, January 5, 2005 -47- Device 0 Function 3 Register Descriptions - DRAM
Offset 69 – DRAM Page Policy Control (00h) ................RW
7-6 Bank Interleave
00 No Interleave..........................................default
01 2-way
10 4-way
11 Reserved
For 16Mb DRAMs bank interleave is always 2-way
5 Reserved ........................................ always reads 0
4 Auto-Precharge for TLB Read or CPU Write-
Back
0 Disable ...................................................default
1 Enable
3 DRAM 8K Page Enable
0 Disable ...................................................default
1 Enable
2 DRAM 4K Page Enable
0 Disable ...................................................default
1 Enable
1 Page Kept Active When Crossing Banks
0 Disable ...................................................default
1 Enable
0 Multiple Page Mode
0 Disable ...................................................default
1 Enable
Offset 6A - Refresh Counter (00h)...................................RW
7-0 Refresh Counter (in units of 16 DRAM clocks)
00 DRAM Refresh Disabled .......................default
01 32 DRAM clocks
02 48 DRAM clocks
03 64 DRAM clocks
04 80 DRAM clocks
05 96 DRAM clocks
… …
The programmed value is the desired number of 16-
DRAM clock units minus one.
Offset 6B - DRAM Arbitration Control (10h)................ RW
7 DQS Input DLL Adjust
0 Disable................................................... default
1 Enable
6 DQS Output DLL Adjust
0 Disable................................................... default
1 Enable
5 Burst Refresh
0 Disable................................................... default
1 Enable
4 Reserved (Do Not Program)................... default = 1
3 HA14 / HA22 Swap
0 Normal................................................... default
1 Swap to improve performance
2-0 SDRAM Operation Mode Select
000 Normal SDRAM Mode ......................... default
001 NOP Command Enable
010 All-Banks-Precharge Command Enable
(CPU-to-DRAM cycles are converted
to All-Banks-Precharge commands).
011 MSR to Low DIMM
100 CBR Cycle Enable (if this code is selected,
CAS-before-RAS refresh is used; if it is not
selected, RAS-Only refresh is used)
101 MSR to High DIMM
11x Reserved