Product specifications

CN333 Data Sheet
Revision 1.0, January 5, 2005 -46- Device 0 Function 3 Register Descriptions - DRAM
Offset 60 – DRAM Control (00h).....................................RW
7 0WS Back-to-Back Write to Different DDR Bank
0 Disable ...................................................default
1 Enable
6 Fast Read to Read Turnaround
0 Disable ...................................................default
1 Enable (DQS postamble overlap with
preamble)
5 Fast Read to Write Turnaround
0 Disable ...................................................default
1 Enable
4 Fast Write to Read Turnaround
0 Disable ...................................................default
1 Enable
3 DQSA Input Capture Extended Range Control
0 .....................................................default
1
2 DQSB Input Capture Extended Range Control
0 .....................................................default
1
1-0 DQS[7:4] Input Capture Extended Range Control
for Channels A and B
00 .....................................................default
01
10
11
Offset 65 - DRAM Arbitration Timer (00h) ...................RW
7-4 AGP Timer (units of 4 DRAM clocks) .... default = 0
3-0 CPU Timer (units of 4 DRAM clocks)..... default = 0
Offset 66 - DRAM Arbitration Control (00h).................RW
7 DRAM Controller Queue Greater Than 2
0 Disable ...................................................default
1 Enable
6 DRAM Controller Queue Not Equal To 4
0 Disable ...................................................default
1 Enable
5-4 Arbitration Parking Policy
00 Park at last bus owner ............................default
01 Park at CPU
10 Park at AGP
11 -reserved-
3-0 AGP / CPU Priority (units of 4 DRAM clocks)
Offset 68 – DRAM DDR Control (00h)........................... RW
7 DRAM Access Timing
0 2T .................................................... default
1 3T
6 Non-Burst Write-to-Write Can Be Closer in Non-
DQM Mode
0 Disable................................................... default
1 Enable
5 Zero Delay DRAM Channel Switching for Read
Cycles
0 Disable................................................... default
1 Enable
4 Zero Delay DRAM Channel Switching for Write
Cycles
0 Disable................................................... default
1 Enable
3-0 DRAM Operating Frequency
CPU / DRAM
0000 133 / 133 (DDR-266)......................... default
0001 100 / 133 (DDR-266)
133 / 166 (DDR-333)
0101 100 / 166 (DDR-333)
1001 -reserved-
0010 -reserved-
1010 -reserved-
All other combinations are reserved.