Product specifications

CN333 Data Sheet
Revision 1.0, January 5, 2005 -45- Device 0 Function 3 Register Descriptions - DRAM
Offset 51-50 - DRAM MA Map Type (2222h) ................RW
15-13 Bank 5/4 MA Map Type (see Table below)
12 Bank 5/4 1T Command Rate
0 2T Command .........................................default
1 1T Command
11-9 Bank 7/6 MA Map Type (see Table below)
8 Bank 7/6 1T Command Rate
0 2T Command .........................................default
1 1T Command
7-5 Bank 1/0 MA Map Type (see Table below)
4 Bank 1/0 1T Command Rate
0 2T Command .........................................default
1 1T Command
3-1 Bank 3/2 MA Map Type (see Table below)
0 Bank 3/2 1T Command Rate
0 2T Command .........................................default
1 1T Command
Table 8. MA Map Type Encoding
000 – -reserved
001 64/128Mb
8 / 9-bit Column Address.........default
010 64/128Mb 9 / 10-bit Column Address
011 64/128Mb
10 / 11-bit Column Address
100 1Gb
10 / 11 / 12-bit Column Address
101 256/512Mb
8-bit Column Address
110 256/512Mb 9-bit Column Address
111 256/512Mb 10 / 11 / 12-bit Column Address
Offset 52 - DRAM Rank End Address Bit-33 (00h).......RW
7-1 Reserved ........................................ always reads 0
0 Rank End Address Bit-33........................ default = 0
Offset 53 - DRAM Rank Begin Address Bit-33 (00h) ....RW
7-1 Reserved ........................................ always reads 0
0 Rank Begin Address Bit-33..................... default = 0
Offset 54 - DRAM Controller Internal Options (00h) ...RW
7-5 Reserved ........................................ always reads 0
4 Read-Modify-Write Option
0 Disable ...................................................default
1 Enable
3 Apply Same-Channel Constraints on Different
Channels
0 Disable ...................................................default
1 Enable
2 Two SCMD Buses Are Exclusive & Cannot
Operate Simultaneously
0 Disable ...................................................default
1 Enable
1-0 Reserved ........................................ always reads 0
Offset 55 - DRAM Rank Decode Address Config (00h) RW
7-2 Reserved ........................................always reads 0
1-0 DRAM Rank Decode Address Configuration
00 .................................................... default
01
10
11
Offset 56 - DRAM Timing for All Banks I (65h) ........... RW
7-6 Active Command to Precharge Command Period
00 T
RAS = 6T
01 TRAS = 7T ............................................. default
10 T
RAS = 8T
11 TRAS = 9T
5-4 CAS Latency
00 1.5T
01 2T
10 2.5T ................................................... default
11 3T
3-2 ACTIVE to CMD
00 T
RCD = 2T
01 T
RCD = 3T ............................................. default
10 TRCD = 4T
11 TRCD = 5T
1-0 Precharge Command to Active Command Period
00 T
RP = 2T
01 TRP = 3T ............................................... default
10 T
RP = 4T
11 TRP = 5T
Offset 57 - DRAM Timing for All Banks II (01h).......... RW
7-6 Reserved ........................................always reads 0
5 Active (0) -> Active (1)
0 T
RRD = 2T .............................................. default
1 TRRD = 3T
4 Write Recovery Time
0 2T .................................................... default
1 3T
3 T
WTR
0 T
WTR = 1T.............................................. default
1 T
WTR = 2T
2 Increase T
RFC For 1 Gbit DRAMs
0 Disable................................................... default
1 Enable
1-0 T
RFC (Refresh-to-Active or Refresh-to-Refresh)
Bit-2=0
Bit-2=1
00 12T 21T
01 13T 22T.................................. default
10 14T 23T
11 15T 24T