Product specifications

CN333 Data Sheet
Revision 1.0, January 5, 2005 -44- Device 0 Function 3 Register Descriptions - DRAM
Device 0 Function 3 Device-Specific Registers
These registers are normally programmed once at system
initialization time.
DRAM Control
These registers are normally set at system initialization time
and not accessed after that during normal system operation.
Some of these registers, however, may need to be programmed
using specific sequences during power-up initialization to
properly detect the type and size of installed memory (refer to
the VIA Technologies CN333 BIOS porting guide for details).
Table 6. System Memory Map
Space
Start Size Address Range Comment
DOS 0 640K 00000000-0009FFFF Cacheable
VGA 640K 128K 000A0000-000BFFFF Used for SMM
BIOS 768K 16K 000C0000-000C3FFF Shadow Ctrl 1
BIOS 784K 16K 000C4000-000C7FFF Shadow Ctrl 1
BIOS 800K 16K 000C8000-000CBFFF Shadow Ctrl 1
BIOS 816K 16K 000CC000-000CFFFF Shadow Ctrl 1
BIOS 832K 16K 000D0000-000D3FFF Shadow Ctrl 2
BIOS 848K 16K 000D4000-000D7FFF Shadow Ctrl 2
BIOS 864K 16K 000D8000-000DBFFF Shadow Ctrl 2
BIOS 880K 16K 000DC000-000DFFFF Shadow Ctrl 2
BIOS 896K 64K 000E0000-000EFFFF Shadow Ctrl 3
BIOS 960K 64K 000F0000-000FFFFF Shadow Ctrl 3
Sys 1MB — 00100000-DRAM Top Can have hole
Bus D Top DRAM Top-FFFEFFFF
Init 4G-64K 64K FFFEFFFF-FFFFFFFF 000Fxxxx alias
Offset 40-47 – DRAM Row Ending Address:
Offset 40 – Bank 0 Ending (HA[32:25]) (01h) ...........RW
Offset 41 – Bank 1 Ending (HA[32:25]) (01h) ...........RW
Offset 42 – Bank 2 Ending (HA[32:25]) (01h) ...........RW
Offset 43 – Bank 3 Ending (HA[32:25]) (01h) ...........RW
Offset 44 – Bank 4 Ending (HA[32:25]) (01h) ...........RW
Offset 45 – Bank 5 Ending (HA[32:25]) (01h) ...........RW
Offset 46 – Bank 6 Ending (HA[32:25]) (01h) ...........RW
Offset 47 – Bank 7 Ending (HA[32:25]) (01h) ...........RW
Note : Refer to the BIOS Porting Guide or BIOS Porting
Update Note for detailed programming information.
Offset 48 - DRAM DIMM #0 Control (00h)................... RW
7 Rank 1 Enable ..........................................default = 0
6 Rank 0 Enable ..........................................default = 0
5 Rank 1 Is Above 4GB............................... default = 0
4 Rank 0 Is Above 4GB............................... default = 0
3-0 MA Setting (see Table below)...................default = 0
Offset 49 - DRAM DIMM #1 Control (00h)................... RW
7 Rank 3 Enable ..........................................default = 0
6 Rank 2 Enable ..........................................default = 0
5 Rank 3 Is Above 4GB............................... default = 0
4 Rank 2 Is Above 4GB............................... default = 0
3-0 MA Setting (see Table below).................default = 0
Offset 4A - DRAM DIMM #2 Control (00h) .................. RW
7 Rank 5 Enable ..........................................default = 0
6 Rank 4 Enable ..........................................default = 0
5 Rank 5 Is Above 4GB............................... default = 0
4 Rank 4 Is Above 4GB............................... default = 0
3-0 MA Setting (see Table below).................default = 0
Offset 4B - DRAM DIMM #3 Control (00h) .................. RW
7 Rank 7 Enable ..........................................default = 0
6 Rank 6 Enable ..........................................default = 0
5 Rank 7 Is Above 4GB............................... default = 0
4 Rank 6 Is Above 4GB............................... default = 0
3-0 MA Setting (see Table below).................. default = 0
Table 7. DIMM MA Setting
Columns 12 Rows 13 Rows 14 Rows
8 0000 – –
32 MB/Rank
9 0001 0100 –
64 MB/Rank 128 MB/Rank
10 0010 0101 1000
128 MB/Rank 256 MB/Rank 512 MB/Rank
11 0011 0110 1001
256 MB/Rank 512 MB/Rank 1 GB/Rank
12 – 0111 1010
1 GB/Rank 2 GB/Rank