Product specifications

CN333 Data Sheet
Revision 1.0, January 5, 2005 -41- Device 0 Function 2 Register Descriptions – Host CPU
Offset 60 – DRDY L Timing Control 1 (00h)..................RW
7-6 Phase 4 L Wait States .......................... default = 00b
5-4 Phase 3 L Wait States .......................... default = 00b
3-2 Phase 2 L Wait States .......................... default = 00b
1-0 Phase 1 L Wait States .......................... default = 00b
Offset 61 – DRDY L Timing Control 2 (00h)..................RW
7-6 Phase 8 L Wait States .......................... default = 00b
5-4 Phase 7 L Wait States .......................... default = 00b
3-2 Phase 6 L Wait States .......................... default = 00b
1-0 Phase 5 L Wait States .......................... default = 00b
Offset 62 – DRDY L Timing Control 3 (00h)..................RW
7-4 Reserved ........................................ always reads 0
3-2 Phase 10 L Wait States ........................ default = 00b
1-0 Phase 9 L Wait States .......................... default = 00b
Offset 63 – DRDY Q Timing Control 1 (00h) .................RW
7-6 Phase 4 Q Wait States.......................... default = 00b
5-4 Phase 3 Q Wait States.......................... default = 00b
3-2 Phase 2 Q Wait States.......................... default = 00b
1-0 Phase 1 Q Wait States.......................... default = 00b
Offset 64 – DRDY Q Timing Control 2 (00h) .................RW
7-6 Phase 8 Q Wait States.......................... default = 00b
5-4 Phase 7 Q Wait States.......................... default = 00b
3-2 Phase 6 Q Wait States.......................... default = 00b
1-0 Phase 5 Q Wait States.......................... default = 00b
Offset 65 – DRDY Q Timing Control 3 (00h) .................RW
7-4 Reserved ........................................ always reads 0
3-2 Phase 10 Q Wait States........................ default = 00b
1-0 Phase 9 Q Wait States.......................... default = 00b
Offset 66 – Burst DRDY Timing Control 1 (00h) .......... RW
7 Burst DRDY Wait State #8
6 Burst DRDY Wait State #7
5 Burst DRDY Wait State #6
4 Burst DRDY Wait State #5
3 Burst DRDY Wait State #4
2 Burst DRDY Wait State #3
1 Burst DRDY Wait State #2
0 Burst DRDY Wait State #1
0 0 ws DRDY Burst.................................. default
1 1 ws DRDY Burst
Offset 67 – Burst DRDY Timing Control 2 (00h) .......... RW
7-6 Reserved ........................................always reads 0
5-4 Burst DRDY Wait State #10-9
0 Disable................................................... default
1 Enable
3-0 Reserved ........................................always reads 0
Offset 68 – Lowest Priority CPU ID #0 (00h).................. RO
Offset 69 – Lowest Priority CPU ID #1 (00h).................. RO
Offset 6A – Lowest Priority CPU ID #2 (00h)................. RO
Offset 6B – Lowest Priority CPU ID #3 (00h)................. RO
Offset 6C – Lowest Priority CPU ID #4 (00h)................. RO
Offset 6D – Lowest Priority CPU ID #5 (00h)................. RO
Offset 6E – Lowest Priority CPU ID #6 (00h)................. RO
Offset 6F – Lowest Priority CPU ID #7 (00h) ................. RO