Product specifications

CN333 Data Sheet
Revision 1.0, January 5, 2005 -40- Device 0 Function 2 Register Descriptions – Host CPU
Offset 59 – IPI Control (00h)............................................RW
7-1 Reserved ........................................ always reads 0
0 Lowest Priority IPI Support
0 Disable ...................................................default
1 Enable
Offset 5A – Destination ID (00h)......................................RW
7-0 Destination ID in A[19:12] .................. default = 00h
Offset 5B – Interrupt Vector (00h) ..................................RW
7-0 Interrupt Vector in D[7:0] .................. default = 00h
Offset 5C – CPU Miscellaneous Control (00h) ...............RW
7 Reserved ........................................ always reads 0
6 Copy / Compare Performance Improvement
0 Disable ...................................................default
1 Enable
5 CPU Bus Ownership
0 Disable ...................................................default
1 Enable
4 Patch D11 in APIC Logic Mode
0 Disable ...................................................default
1 Enable
3 Redirection Hint Information Obtained From
0 Address Field .........................................default
1 Data Field
2 Destination Mode Information Obtained From
0 Address Field .........................................default
1 Data Field
1 APIC Cluster Mode Support
0 Disable ...................................................default
1 Enable
0 Reserved ........................................ always reads 0
Offset 5D – Write Policy (00h) .........................................RW
7-4 Write Request Limit.............................. default = 0h
3-0 Write Request Base................................ default = 0h
Offset 5E – Bandwidth Timer (00h) ................................RW
7-4 Host CPU Bandwidth Timer................. default = 0h
3-0 DRAM Bandwidth Timer ..................... default = 0h
Offset 5F – CPU Miscellaneous Control (00h) ............... RW
7 Same Bank But Different Sub-Bank Considered
Off-Page
0 Disable................................................... default
1 Enable (reduces post-write burst length and
may increase performance)
6 Back-to-Back Fast Read, Burst CPU-to-AGP
Read and Burst CPU-to-Memory Read
0 Disable................................................... default
1 Enable
5 Machine Error Output
0 Disable................................................... default
1 Enable
4 Bus Initialization Output
0 Disable................................................... default
1 Enable
3 Pipeline APIC / Master Transactions
0 Disable................................................... default
1 Enable
2 Host CPU Bandwidth Limited
0 Disable................................................... default
1 Enable
1 DRAM Bandwidth Limited
0 Disable................................................... default
1 Enable
0 Improve CPU Access DRAM Read After Write
0 Disable................................................... default
1 Enable