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CN333 Data Sheet

Revision 1.0, January 5, 2005 -39- Device 0 Function 2 Register Descriptions – Host CPU

Offset 54 – CPU Frequency (00h) ....................................RW

7-5 CPU FSB Frequency........ Set from VD4,1,0 Straps

000 100 MHz (all three straps pulled low)

001 133 MHz

010 -reserved-

011 -reserved-

100 -reserved-

101 -reserved-

110 -reserved-

111 Auto

4 SDRAM Burst Length of 8

0 Disable ...................................................default

1 Enable (must be set for 128-bit operation)

3 Fast Host Master Read Ready

0 Disable (normal) ....................................default

1 Enable (1T early)

2 PCI Master 8QW Operation

0 Disable ...................................................default

1 Enable

1 Sync 1T Conversion

0 Transparent ............................................default

1 Sync

0 VPX Mode

0 Disable (AGP Mode) .............................default

1 Enable (VPX Mode)

Offset 55 – CPU Miscellaneous Control (00h) ................RW

7-6 Snoop Queue

00 12-level ..................................................default

01 13-level

1x 16-level

5 Reserved ........................................ always reads 0

4 Fast Command with 8QW Prefetch

0 Disable ...................................................default

1 Enable

3 Reserved ........................................ always reads 0

2 Medium Threshold for Write Policy

0 Disable ...................................................default

1 Enable

1 DRDY Early / Late Timing Select

0 2T Early .................................................default

1 2T Late

0 Reserved ........................................ always reads 0

Offset 56 – Reorder Latency (00h) .................................. RW

7-4 Medium Threshold for Write Policy to Improve

Memory Read / Write Performance

A setting of 2-4 is recommended .............default = 0h

3-0 Maximum Reorder Latency

0000 Disable (same as Rx55[0]=0) ................ default

0001 Reorder latency 1 (Rx55[0] must be 1)

0010 Reorder latency 2 (Rx55[0] must be 1)

… …

1100 Reorder latency 12 (Rx55[0] must be 1)

1101 -reserved-

1110 -reserved-

1111 -reserved-

Offset 58 – Delivery / Trigger Control (00h) .................. RW

7 Redirection Hint in Register-Triggered APIC