Product specifications

CN333 Data Sheet
Revision 1.0, January 5, 2005 -38- Device 0 Function 2 Register Descriptions – Host CPU
Device 0 Function 2 Device-Specific Registers
These registers are normally programmed once at system
initialization time.
Host CPU Control
Offset 50 – Request Phase Control (00h) ........................RW
7 CPU Hardwired IOQ (In Order Queue) Size
Default set from the inverse of the VD2 strap. This
register can be written 0 to restrict the chip to one
level of IOQ.
0 1-Level (strap pulled high)
1 8-Level (strap pulled low)
6 Dual CPU Support
Default set from the VD7 strap (VT8237R South
Bridge PDCS3# pin) or ROMSIP.
0 Single (SB strap pulled low)
1 Dual (SB strap pulled high)
5 Fast DRAM Access
0 Disable ...................................................default
1 Enable
4-0 Dynamic Defer Snoop Stall Count
(granularity = 2T, normally set to 01000b)
Offset 51 – CPU Interface Basic Control (00h) ..............RW
7 CPU Read DRAM Fast Ready
0 Wait until all 8 QWs are received before
DRDY is returned ..................................default
1 See Rx60-67 for DRDY timing
6 Read Around Write
0 Disable ...................................................default
1 Enable
5 DRQ Control
0 Non pipelined similar to Pro266 ............default
1 Pipelined
4 CPU to PCI Read Defer
0 Disable ...................................................default
1 Enable
3 Two Defer / Retry Entries
0 Disable ...................................................default
1 Enable
2 Two Defer / Retry Entries Shared
0 Each entry is dedicated to 1 CPU...........default
1 Each entry is shared by 2 CPUs
1 PCI Master Pipelined Access
0 Disable ...................................................default
1 Enable
0 Reserved ........................................ always reads 0
Offset 52 – CPU Interface Advanced Ctrl (00h) ............ RW
7 CPU RW DRAM 0WS for Back-to-Back Pipeline
Access
0 Disable................................................... default
1 Enable
6 HREQ High Priority
0 Disable................................................... default
1 Enable
5 AGTL+ Pullups
Default set from the inverse of the VD3 strap.
0 Disable (strap pulled high)
1 Enable (strap pulled low)
4 Reserved ........................................always reads 0
3 Write Retire Policy After 2 Writes
0 Disable................................................... default
1 Enable
2 2-Level Defer Queue with Lock
0 Normal Operation.................................. default
1 Enhanced Operation (this bit should always be
set to 1)
1 Consecutive Speculative Read
0 Disable................................................... default
1 Enable
0 Speculative Read
0 Disable................................................... default
1 Enable
Offset 53 – CPU Arbitration Control (00h).................... RW
7-4 Host Timer .............................................. default = 0
3-0 BPRI Timer (units of 4 HCLKs) ..............default = 0