Product specifications

CN333 Data Sheet
Revision 1.0, January 5, 2005 -29- Register Summary Tables
Device 1 Registers - PCI-to-PCI Bridge
Header Registers
Offset
Configuration Space Header Default Acc
1-0 Vendor ID
1106
RO
3-2 Device ID
B198
RO
5-4 Command
0007 RW
7-6 Status
0230 WC
8 Revision ID
nn
RO
9 Program Interface 00 RO
A Sub Class Code
04
RO
B Base Class Code
06
RO
C -reserved- (Cache Line Size) 00 —
D -reserved- (Latency Timer) 00 —
E Header Type
01
RO
F -reserved- (Built In Self Test) 00 —
13-10 Graphics Aperture Base
0000 0008 RW
14-17 -reserved- 00 —
18 Primary Bus Number 00
RW
19 Secondary Bus Number 00
RW
1A Subordinate Bus Number 00
RW
1B -reserved- 00 —
1C I/O Base
F0 RW
1D I/O Limit 00
RW
1F-1E Secondary Status 0000 RO
21-20 Memory Base
FFF0 RW
23-22 Memory Limit (Inclusive) 0000
RW
25-24 Prefetchable Memory Base
FFF0 RW
27-26 Prefetchable Memory Limit 0000
RW
28-33 -reserved- 00 —
34 Capability Pointer
70
RO
35-3F -reserved- 00 —
Device-Specific Registers
Offset
AGP Bus Control Default Acc
40 CPU-to-AGP Flow Control 1 00 RW
41 CPU-to-AGP Flow Control 2
08
RW
42 AGP Master Control 00 RW
43 AGP Master Latency Timer
22
RW
44 Reserved (Do Not Program)
20
RW
45 Fast Write Control
72
RW
47-46 PCI-to-PCI Bridge Device ID 0000 RW
48-6F -reserved- 00 —
Offset
Power Management Default Acc
70 Capability ID
01 RO
71 Next Pointer 00
RO
72 Power Management Capabilities 1
02 RO
73 Power Management Capabilities 2 00
RO
74 Power Management Control / Status 00 RW
75 Power Management Status 00
RO
76 PCI-PCI Bridge Support Extensions 00
RO
77 Power Management Data 00
RO
78-FF -reserved- 00 —