Product specifications
CN333 Data Sheet
Revision 1.0, January 5, 2005 -27- Register Summary Tables
Function 3 DRAM Device-Specific Registers (continued)
Offset
Graphics Control Default Acc
B0 Graphics Control 1 00 RW
B1 Graphics Control 2 00 RW
B2 Graphics Control 3 00 RW
B3 Graphics Control 4 00 RW
B4 Graphics Control 5 00 RW
B5-BF -reserved- 00 —
Offset
AGP Controller Interface Control Default Acc
C0 AGP Controller Interface Control 00 RW
C1-DF -reserved- 00 —
Offset
DRAM Drive Control Default Acc
E0 DRAM DQSA Drive 00 RW
E1 DRAM DQSB Drive 00 RW
E2 DRAM MDA / DQMA Drive 00 RW
E3 DRAM MDB / DQMB Drive 00 RW
E4 DRAM CS / CKE Drive 00 RW
E5 -reserved- 00 —
E6 DRAM S-Port Drive Control 00 RW
E7 -reserved- 00 —
E8 DRAM MAA / ScmdA Drive 00 RW
E9 -reserved- 00 —
EA DRAM MAB / ScmdB Drive 00 RW
EB -reserved- 00 —
EC Channel A Duty Cycle Control 00 RW
ED Channel B Duty Cycle Control 00 RW
EE DDR CKG Duty Cycle Control 1 00 RW
EF DDR CKG Duty Cycle Control 2 00 RW
F0-FF -reserved- 00 —
Device 0 Function 4 Registers – Power Management
Header Registers
Offset
Configuration Space Header Default Acc
1-0 Vendor ID
1106
RO
3-2 Device ID for Power Manager
4259
RO
5-4 Command
0006 RW
7-6 Status
0200 WC
8 Revision ID
0n
RO
9 Program Interface 00 RO
A Sub Class Code 00 RO
B Base Class Code
06
RO
C -reserved- (Cache Line Size) 00 —
D -reserved- (Latency Timer) 00 —
E -reserved- (Header Type) 00 —
F -reserved- (Built In Self Test) 00 —
10-3F -reserved- 00 —
Device-Specific Registers
Offset
Reserved Default Acc
40-4F -reserved- 00 —
50-5F -reserved- 00 —
60-6F -reserved- 00 —
70-7F -reserved- 00 —
80-8F -reserved- 00 —
90-9F -reserved- 00 —
Offset
Power Management Control Default Acc
A0 Power Management Mode 00 RW
A1 DRAM Power Management 00 RW
A2 Dynamic Clock Stop 00 RW
A3 MA / SCMD Pad Toggle Reduction 00 RW
A4-AF -reserved- 00 —
Offset
Reserved Default Acc
B0-BF -reserved- 00 —
C0-CF -reserved- 00 —
Offset
BIOS Scratch Default Acc
D0-EF BIOS Scratch Registers 00 RW
Offset
Test Default Acc
F0-FF Reserved (Do Not Program) 00 RW