Product specifications

CN333 Data Sheet
Revision 1.0, January 5, 2005 -26- Register Summary Tables
Device 0 Function 3 Registers – DRAM
Header Registers
Offset
Configuration Space Header Default Acc
1-0 Vendor ID
1106
RO
3-2 Device ID for DRAM Control
3259
RO
5-4 Command
0006 RW
7-6 Status
0200 WC
8 Revision ID
0n
RO
9 Program Interface 00 RO
A Sub Class Code 00 RO
B Base Class Code
06
RO
C -reserved- (Cache Line Size) 00 —
D -reserved- (Latency Timer) 00 —
E -reserved- (Header Type) 00 —
F -reserved- (Built In Self Test) 00 —
10-2B -reserved- 00 —
2D-2C Subsystem Vendor ID 00
W1
2F-2E Subsystem ID 00
W1
30-33 -reserved- 00 —
37-34 Capability Pointer 0000 0000 RO
38-3F -reserved- 00 —
Device-Specific Registers
Offset
DRAM Control Default Acc
40-47 DRAM Row Ending Address:
40 Bank 0 Ending (HA[32:25])
01
RW
41 Bank 1 Ending (HA[32:25])
01
RW
42 Bank 2 Ending (HA[32:25])
01
RW
43 Bank 3 Ending (HA[32:25])
01
RW
44 Bank 4 Ending (HA[32:25])
01
RW
45 Bank 5 Ending (HA[32:25])
01
RW
46 Bank 6 Ending (HA[32:25])
01
RW
47 Bank 7 Ending (HA[32:25])
01
RW
48 DRAM DIMM #0 Control 00 RW
49 DRAM DIMM #1 Control 00 RW
4A DRAM DIMM #2 Control 00 RW
4B DRAM DIMM #3 Control 00 RW
4C-4F -reserved- 00 —
51-50 MA Map Type
2222
RW
52 DRAM Rank End Address Bit-33 00 RW
53 DRAM Rank Begin Address Bit-33 00 RW
54 DRAM Controller Internal Options 00 RW
55 DRAM Timing for All Banks I 00 RW
56 DRAM Timing for All Banks II
65
RW
57 DRAM Timing for All Banks III
01
RW
58-5F -reserved- 00 —
60 DRAM Control 00 RW
61-64 -reserved- 00 —
65 DRAM Arbitration Timer 00 RW
66 DRAM Arbitration Control 00 RW
67 Reserved (Do Not Program) 00 RW
68 DRAM DDR Control 00 RW
Device-Specific Registers (continued)
Offset
Reserved Default Acc
69 DRAM Page Policy Control 00 RW
6A DRAM Refresh Counter 00 RW
6B DRAM Arbitration Control
10
RW
6C DRAM Clock Control 00 RW
6D -reserved- 00 —
6E DRAM Control 00 RW
6F -reserved- 00 —
70 DRAM DDR Control 1 00 RW
71 DRAM DDR Control 2 00 RW
72 DRAM DDR Control 3 00 RW
73 DRAM DDR Control 4 00 RW
74 DRAM DQS Input Delay 00 RW
75 -reserved- 00 —
76 DRAM Early Clock Select 00 RW
77 -reserved- 00 —
78 DRAM Timing Control
13
RW
79 DRAM DQS Output Control
01
RW
7A DRAM DQS Capture Control Chan A
44
RW
7B DRAM DQS Capture Control Chan B
04
RW
7C DIMM0 DQS Input Delay Offset 00 RW
7D DIMM1 DQS Input Delay Offset 00 RW
7E DIMM2 DQS Input Delay Offset 00 RW
7F DIMM3 DQS Input Delay Offset 00 RW
Offset
ROM Shadow Default Acc
80 C-ROM Shadow Control 00 RW
81 D-ROM Shadow Control 00 RW
82 F-ROM Shadow/MemHole/SMI Ctrl 00 RW
83 E-ROM Shadow Control 00 RW
Offset
DRAM Above 4G Control Default Acc
84 Low Top Address Low 00 RW
85 Low Top Address High
FF
RW
86 SMM / APIC Decoding
01
RW
87-9F -reserved- 00 —
Offset
UMA Control Default Acc
A0 CPU Direct Access FB Base 00 RW
A1 CPU Direct Access FB Size 00 RW
A2 VGA Timer 00 RW
A3 Graphics Timer 00 RW
A4 Graphics Miscellaneous Control 00 RW
A5-AF -reserved- 00 —