Product specifications

CN333 Data Sheet
Revision 1.0, January 5, 2005 -22- Pin Descriptions
Strap Pin Descriptions
Strap Pins
(External pullup / pulldown straps are required to select “H” / “L”)
Signal
Actual
Strap Pin
Function Description Status Bit
VD7
VT8235M-CD:
SDCS3#
VT8235M-CE:
SDCS3#
VT8237R:
PDCS3#
Number of
processors
installed
L: Single processor
H: Dual processor
VD7 is sampled during system initialization; the
actual strapping pin is located on the South Bridge
chip.
F2Rx50[6]
VD6
VT8235M-CD:
SDA2
VT8235M-CE:
SDA2
VT8237R:
PDA2
Auto-Configure L: Disable Auto-Configure
H: Enable Auto-Configure
VD6 is sampled during system initialization; the
actual strapping pin is located on the South Bridge
chip.
F2Rx76[2]
VD5
VT8235M-CD:
SDA1
VT8235M-CE:
SDA1
VT8237R:
PDA1
-reserved- Must be strapped high.
VD5 is sampled during system initialization; the
actual strapping pin is located on the South Bridge
chip.
-
VD3
VT8235M-CD:
SA19
VT8235M-CE:
Strap_VD3
VT8237R:
GPIOD
AGTL+ Pullups L: Enable internal AGTL+ Pullups
H: Disable internal AGTL+ Pullups
VD3 is sampled during system initialization; the
actual strapping pin is located on the South Bridge
chip.
F2Rx52[5]
VD2
VT8235M-CD:
SA18
VT8235M-CE:
Strap_VD2
VT8237R:
GPIOB
IOQ Depth L: 8-Level deep
H: 1-Level deep
VD2 is sampled during system initialization; the
actual strapping pin is located on the South Bridge
chip.
F2Rx50[7]
VD4, VD1, VD0
VT8235M-CD:
SDA0, SA17, SA16
VT8235M-CE:
SDA0, Strap_VD1,
Strap_VD0
VT8237R:
PDA0, GPIOA,
GPIOC
FSB Frequency LLL: 100MHz LLH: 133MHz
LHL: -reserved- LHH: -reserved-
HLL: -reserved- HLH: -reserved-
HHL: -reserved- HHH: Auto
VD4, VD1 and VD0 are sampled during system
initialization; the actual strapping pins are located on
the South Bridge chip.
F2Rx54[7:5]