Product specifications

CN333 Data Sheet
Revision 1.0, January 5, 2005 -19- Pin Descriptions
Clock, Reset, Power Control, GPIO, Interrupt and Test Pin Descriptions
Clocks, Resets, Power Control, General Purpose I/O, Interrupts and Test
Signal Name Pin # I/O Signal Description Power Plane
HCLK+
N5 I Host Clock. This pin receives the host CPU clock (100 / 133 / 200
MHz). This clock is used by all CN333 logic that is in the host CPU
domain.
VTT
HCLK–
N6 I
Host Clock Complement. VTT
MCLKO
F30 O Memory (SDRAM) Clock. Output from internal clock generator to
the external clock buffer for memory interface.
VCC25MEM
MCLKI
F29 I Memory (SDRAM) Clock Feedback. Input from MCLKO.
VCC25MEM
DISPCLKI
P2 I Dot Clock (Pixel Clock) In. Used for external EMI reduction circuit
if used. Connect to GND if external EMI reduction circuit not
implemented.
VCC33GFX
DISPCLKO
P3 O Dot Clock (Pixel Clock) Out. Used for external EMI reduction
circuit if used. NC if external EMI reduction circuit not implemented.
VCC33GFX
GCLK
P6 I AGP Clock. Clock for AGP logic.
VCC15AGP
XIN
P7 I Reference Frequency Input. External 14.31818 MHz clock source.
All internal graphics controller clocks are synthesized on chip using
this frequency as a reference.
VCC33GFX
RESET#
AH21 I Reset. Input from the South Bridge chip. When asserted, this signal
resets the CN333 and sets all register bits to the default value. The
rising edge of this signal is used to sample all power-up strap options
VSUS15
PWROK
AG21 I Power OK. Connect to South Bridge and Power Good circuitry.
VSUS15
SUSST#
AJ21 I Suspend Status. For implementation of the Suspend-to-DRAM
feature. Connect to an external pull-up to disable.
VSUS15
AGPBUSY# / NMI AE21 O AGP Interface Busy. Connect to a South Bridge GPIO pin for
monitoring the status of the internal AGP bus. See Design Guide for
details. Pin function selectable with Device 0 Function 0 RxBE[7]
(default = NMI).
VCC25MEM
GPOUT / CAPD14 U7 O General Purpose Output. This pin reflects the state of SRD[0].
VCC33GFX
GPO0 / CAPD15 AA2 O General Output Port. When SR1A[4] is cleared, this pin reflects the
state of CR5C[0].
VCC33GFX
INTA#
V5 O Interrupt. PCI interrupt output (handled by the interrupt controller in
the South Bridge)
VCC33GFX
TCLK
N7 I Test Clock. This pin is used for testing and must be connected to
GND through a 1K-4.7K ohm resistor for all board designs.
VCC33GFX
TESTIN#
F27 I Test In. This pin is used for testing and must be connected to VTT
through a 1K-4.7K ohm resistor for all board designs.
VCC25MEM
DFTIN#
F28 I DFT In. This pin is used for testing and must be connected to VTT
through a 1K-4.7K ohm resistor for all board designs.
VCC25MEM
BISTIN / CAPAFLD U6 I BIST In. This pin is used for testing and must be tied to GND with a
1K-4.7K ohm resistor on all board designs.
VCC33GFX