Product specifications

CN333 Data Sheet
Revision 1.0, January 5, 2005 -17- Pin Descriptions
Flat Panel Display Port (FPDP) Pin Descriptions
The FPDP can be configured as either an LVDS transmitter interface port (see the LVDS Transmitter Interface)
24-Bit / Dual 12-Bit Flat Panel Display Interface
Signal Name Pin # I/O Signal Description
FPD23 / FPD0D11
FPD22 / FPD0D10
FPD21 / FPD0D09
FPD20 / FPD0D08
FPD19 / FPD0D07
FPD18 / FPD0D06
FPD17 / FPD0D05
FPD16 / FPD0D04
FPD15 / FPD0D03
FPD14 / FPD0D02
FPD13 / FPD0D01
FPD12 / FPD0D00
FPD11 / FPD1D11
FPD10 / FPD1D10
FPD09 / FPD1D09
FPD08 / FPD1D08
FPD07 / FPD1D07
FPD06 / FPD1D06
FPD05 / FPD1D05
FPD04 / FPD1D04
FPD03 / FPD1D03
FPD02 / FPD1D02
FPD01 / FPD1D01
FPD00 / FPD1D00
AG9
AG10
AJ9
AE12
AK7
AH7
AG7
AK6
AK5
AJ6
AE8
AK4,
AG11
AE11
AF13
AK12
AF12
AH12
AJ12
AK11
AJ10
AH11
AH10
AK9
O Flat Panel Data. For 24-bit or dual 12-bit flat panel display modes.
Two FPD interface modes, 24-bit and dual 12-bit, are supported.
Strap High (3C5.12[4]=1): 24-bit
Strap Low (3C5.12[4]=0): Dual 12-bit
In “24-bit” mode, only one set of control pins is required. However, in
dual 12-bit mode, the CN333 provides two sets of control signals that
are required for certain LVDS transmitter chips.
In 24-bit mode, two operating modes are supported:
3C5.12[4]=1 & 3x5.88[2]=0 & 3x5.88[4]=0
Double data rate: each rising and falling clock edge transmits a
complete 24-bit pixel.
3C5.12[4]=1 & 3x5.88[2]=0 & 3x5.88[4]=1
Single data rate: each clock rising edge transmits a complete 24-bit pixel.
In dual 12-bit mode,
3C5.12[4]=0 & 3x5.88[2] = 1
Double data rate: Each rising and falling clock edge transmits half (12
bits) of two 24-bit pixels.
FPHS
AE9 O Flat Panel Horizontal Sync. 24-bit mode or port 0 in dual 12-bit mode.
FPVS
AJ7 O Flat Panel Vertical Sync. 24-bit mode or port 0 in dual 12-bit mode.
FPDE
AF7 O Flat Panel Data Enable. 24-bit mode or port 0 in dual 12-bit mode.
FPDET
AJ4 I Flat Panel Detect. 24-bit mode or port 0 in dual 12-bit mode.
FPCLK
AE7 O Flat Panel Clock. 24-bit mode or port 0 in dual 12-bit mode.
FPCLK# AE3 O Flat Panel Clock Complement. 24-bit mode or port 0 in dual 12-bit
mode. For double-data-rate data transfers.
FP1HS
AK10 O Flat Panel Horizontal Sync. For port 1 in dual 12-bit mode.
FP1VS
AE10 O Flat Panel Vertical Sync. For port 1 in dual 12-bit mode.
FP1DE
AG8 O Flat Panel Data Enable. For port 1 in dual 12-bit mode.
FP1DET
AF10 I Flat Panel Detect. For port 1 in dual 12-bit mode.
FP1CLK
AG12 O Flat Panel Clock. For port 1 in dual 12-bit mode.
FP1CLK#
AF9 O Flat Panel Clock Complement. For port 1 in dual 12-bit mode. For
double-data-rate data transfers.
Flat Panel Power Control
Signal Name Pin # I/O Signal Description
ENAVDD
AE4 IO
Enable Panel VDD Power.
ENAVEE
AD5 IO
Enable Panel VEE Power.
ENABLT
AE5 IO
Enable Panel Back Light.
Note: I/O pads for all pins on this page are powered by VCC15AGP (i.e., 1.5V I/O).