Product specifications

CN333 Data Sheet
Revision 1.0, January 5, 2005 -16- Pin Descriptions
CRT and Serial Bus Pin Descriptions
CRT Interface
Signal Name Pin # I/O Signal Description
AR
T3 AO Analog Red. Analog red output to the CRT monitor.
AG
T2 AO Analog Green. Analog green output to the CRT monitor.
AB
T1 AO Analog Blue. Analog blue output to the CRT monitor.
HSYNC
V1 O Horizontal Sync. Output to CRT.
VSYNC
V2 O Vertical Sync. Output to CRT.
RSET
V4 AI Reference Resistor. Tie to GNDDAC through an external
82Ω 1% resistor to control the RAMDAC full-scale current value.
I/O pads for the pins in the above table are powered by VCC33GFX (i.e., 3.3V I/O).
SMB / I2C Interface
Signal Name Pin # I/O Signal Description
SBPLCLK
AH8 IO
I2C Serial Bus Clock for Panel
SBPLDAT
AH9 IO
I2C Serial Bus Data for Panel
SBDDCCLK
AD4 IO
I2C Serial Bus Clock for CRT DDC
SBDDCDAT
AD3 IO
I2C Serial Bus Data for CRT DDC
SPCLK2
SPCLK1 / CAPD12
SPDAT2,
SPDAT1 / CAPD13
W2, AB2
V3, AB3
IO Serial Port (SMB/I2C) Clock and Data. The SPCLKn pins are the
clocks for serial data transfer. The SPDATn pins are the data signals used
for serial data transfer. SPxxx1 is typically used for DVI monitor
communications and SPxxx2 is typically used for DDC for CRT monitor
communications. These pins are programmed via “Sequencer” graphics
registers (port 3C5) in the “Extended” VGA register space (see the
UniChrome-II Graphics Registers document for additional details). The
SPxxx1 registers are programmed via 3C5.31 (“IIC Serial Port Control 1”)
and the SPxxx2 registers are programmed via 3C5.26 (“IIC Serial Port
Control 0”). In both registers, the clock out state is programmed via bit-5
and the data out state via bit-4, clock in status may be read in bit-3 and data
in status in bit-2 and the port may be enabled via bit-0.
I/O pads for SPCLK[2:1] / SPDAT[2:1] above are powered by VCC33GFX (i.e., 3.3V I/O).
All other pins in the above table are powered by VCC15AGP (i.e., 1.5V I/O).