Product specifications

CN333 Data Sheet
Revision 1.0, January 5, 2005 -14- Pin Descriptions
The pinouts were defined assuming the ATX PCB layout model shown below (and general pin layout shown) as a guide for PCB
component placement. Other PCB layouts (AT, LPX and NLX) were also considered and can typically follow the same general
component placement.
DDR SDRAM Memory Controller Pin Descriptions
DDR DRAM Interface
Signal Name Pin # I/O Signal Description
MA[13:0]
(see pin lists) O Memory Address. Output drive strength may be set by Device 0
Function 3 RxE8.
BA[1:0]
AB27, AB26 O Bank Address. Output drive strength may be set by Device 0 Function
3 RxE8.
SRAS#, SCAS#, SWE# AG27, AG26, AF25 O
Row Address, Column Address and Write Enable Command
Indicators. Output drive strength may be set by Device 0 Function 3
Rx E8.
MD[63:0]
(see pin lists) IO Memory Data. These signals are connected to the DRAM data bus.
Output drive strength may be set by Device 0 Function 3 RxE2.
DQM[7:0]
AK24, AK29,
AG29, AC28, Y30,
T29, M28, J30
O Data Mask. Data mask of each byte lane. Output drive strength may
be set by Device 0 Function 3 RxE2.
DQS[7:0]# AJ24, AK28, AF30,
AC30, W29, T30,
M29, J29
IO DDR Data Strobe. Data strobe of each byte lane. Output drive
strength may be set by Device 0 Function 3 RxE0.
CS[3:0]#
AG23, AG25,
AH25, AH26
O Chip Select. Chip select of each bank. Output drive strength may be
set by Device 0 Function 3 RxE4.
CKE[3:0]
K27, M27, K28,
M26
O Clock Enables. Clock enables for each DRAM bank for powering
down the SDRAM or clock control for reducing power usage and for
reducing heat / temperature in high-speed memory systems.
Note: I/O pads for all pins on this page are powered by VCC25MEM. MD / DQS input voltage levels are referenced to
MEMVREF.
1 … 36
DDR
SDRAM
Modules
IDE Connectors
PCI Slots
VT8237R
V-Link
South
Bridge
Power
Supply
AGP
A
…
AT
VL
VIA C3
CPU
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CPU
CN
333
GFX