Product specifications

CN333 Data Sheet
Revision 1.0, January 5, 2005 -13- Pin Descriptions
Pin Descriptions
CPU Interface Pin Descriptions
CPU Interface
Signal Name Pin # I/O Signal Description
HA[31:3]#
(see pin list) IO Host Address Bus. HA[31:3] connect to the address bus of the host CPU. During
CPU cycles HA[31:3] are inputs. These signals are driven by the North Bridge during
cache snooping operations.
HD[63:0]#
(see pin list) IO Host CPU Data. These signals are connected to the CPU data bus.
ADS#
A28 IO Address Strobe. The CPU asserts ADS# in T1 of the CPU bus cycle.
BNR#
A21 IO Block Next Request. Used to block the current request bus owner from issuing new
requests. This signal is used to dynamically control the processor bus pipeline depth.
BPRI#
B23 IO Priority Agent Bus Request. The owner of this signal will always be the next bus
owner. This signal has priority over symmetric bus requests and causes the current
symmetric owner to stop issuing new transactions unless the HLOCK# signal is
asserted. The North Bridge drives this signal to gain control of the processor bus.
DBSY#
B26 IO Data Bus Busy. Used by the data bus owner to hold the data bus for transfers requiring
more than one cycle.
DEFER#
A24 IO Defer. A dynamic deferring policy is used to optimize system performance. The
DEFER# signal is also used to indicate a processor retry response.
DRDY#
A27 IO Data Ready. Asserted for each cycle that data is transferred.
HIT#
E25 IO Hit. Indicates that a caching agent holds an unmodified version of the requested line.
Also driven in conjunction with HITM# by the target to extend the snoop window.
HITM#
B25 I Hit Modified. Asserted by the CPU to indicate that the address presented with the last
assertion of EADS# is modified in the L1 cache and needs to be written back.
HLOCK#
E24 I Host Lock. All CPU cycles sampled with the assertion of HLOCK# and ADS# until
the negation of HLOCK# must be atomic.
HREQ[4:0]#
C23, D24, B24,
C22, A25
IO Request Command. Asserted during both clocks of the request phase. In the first
clock, the signals define the transaction type to a level of detail that is sufficient to
begin a snoop request. In the second clock, the signals carry additional information to
define the complete transaction type.
HTRDY#
D25 IO Host Target Ready. Indicates that the target of the processor transaction is able to
enter the data transfer phase.
RS[2:0]#
B27, C25, C26 IO Response Signals. Indicates the type of response per the table below:
RS[2:0]# Response type
000 Idle State
001 Retry Response
010 Defer Response
011 Reserved
100 Hard Failure
101 Normal Without Data
110 Implicit Writeback
111 Normal With Data
CPURST#
D16 O CPU Reset. Reset output to CPU. External pullup and filter capacitor to ground
should be provided per CPU manufacturer’s recommendations.
BREQ0#
C27 O Bus Request 0. Connect to CPU bus request 0.
Note: Clocking of the CPU interface is performed with HCLK+ and HCLK–.
Note: Internal pullup resistors are provided on all GTL interface pins. If the CPU does not have internal pullups, the North
Bridge internal pullups may be enabled to allow the interface to meet GTL bus interface specifications (see strap
descriptions).
Note: I/O pads for the above pins are powered by VTT. Input voltage levels are referenced to HAVREF, HDVREF and
GTLREF.