Product specifications

CN333 Data Sheet
Revision 1.0, January 5, 2005 -7- Overview
24-Bit FPD
plus 12-Bit DVP
66 MHz PCI Host Bus Interface
Me m ory I nt e rface Unit
VGA GFX Controller
Command Engine
128-bit 2D Engine
MP EG En g i n e
Video Processor
GFX Stre am
HW Cursor
Video Engine
0/1
(Scaler /
YUV-to-RGB)
Video Stream
HW Sprite
IGA 1
IGA 2
Digital Video
Port 1
Panel
DAC
CRT
North Bridge M e mory Controlle r
North Bridge Host Bus
Vertex
Cache
Setup
En g i n e
Te xt u re
Eng i n e
Te xt u re
Cache
Rendering
Pipelines
AGP-lik e Interface
3D Engine
Display
Engine
Digital Video
Port
Mux
Figure 2. Integrated UniChrome Pro Graphics Controller Internal Block Diagram
LCD and DVI Monitor Support
The CN333 provides two “Digital Video Port” interfaces: FPDP and GDVP1. The Flat Panel Display Port (FPDP) implements a
24-bit / dual 12-bit interface which is designed to drive a Flat Panel Display via an external LVDS transmitter chip (such as the
VIA VT1631 or NSC DS90C387R). The CN333 can be connected to the external LVDS transmitter chip in either 24-bit or dual-
12-bit modes. A wide variety of LCD panels are supported including VGA, SVGA, XGA, SXGA+ and up to UXGA-resolution
TFT color panels, in either SDR (1 pixel / clock) or DDR (2 pixels / clock) modes. UXGA and higher resolutions require dual-
edge data transfer (DDR) mode which is supported by the VIA VT1631 LVDS transmitter chip. Digital Video Port 1 (GDVP1) is
used to drive a DVI monitor via an external DVI transmitter chip (such as the VIA VT1632A).
The flexible display configurations of the CN333 allow support of a flat panel (LVDS interface) or flat panel monitor (DVI
interface) and CRT display at the same time. Internally the CN333 North Bridge provides two separate display engines, so if two
display devices are connected, each can display completely different information at different resolutions, pixel depths and refresh
rates. If more than two display devices are connected, the additional displays must have the same resolution, pixel depth and
refresh rate as one of the first two. The maximum display resolutions supported for one display device are listed in the table below.
If more than one display is implemented (i.e., if both display engines are functioning at the same time), then available memory
bandwidth may limit the display resolutions supported on one or both displays. This will be dependent on many factors including
primarily clock rates and memory speeds (contact VIA for additional information).