Product specifications

CN333 Data Sheet
Revision 1.0, January 5, 2005 -5- Overview
CN333 SYSTEM OVERVIEW
The CN333 is a high performance, cost-effective and energy efficient UMA North Bridge with integrated UniChrome Pro graphics
/ video controller used for the implementation of mobile and desktop personal computer systems with 133 / 100 MHz CPU host
bus (“Front Side Bus”) based on VIA C3 processors.
RGB, HV, DDC
CRT
VT1631 LVDS
Transmitter
TFT Flat Panel
6X
USB 2.0
DVI Monitor
VT1632A DVI
Transmitter
GDVP1 Digital Video Port 1
12-Bit DVI Interface
LPC
EPROM
Pri
Sec
133 / 100 MHz
Front Side Bus
VIA C3
CPU
64-Bit DDR333 / 266 DIMMs
PCI Slots
CN333
DDR North Bridge
with UniChrome Pro
Graphics Controller
33MHz,
32-bit
PCI
66 MHz 8x / 4x V-Link
AC-Link
VT1616
AC'97 Audio Codec
MC-97
Modem Codec
UDMA / ATA
133 / 100 / 66 / 33
Integrated
AC'97 Audio
Network
Interface PHY
VT1211
LPC
Super
I/O
Keyboard
System
Management
Bus
10/100 Ethernet
Serial / IR
Parallel
Floppy Disk
MII
Mouse
FPDP Flat Panel Display Port
24-Bit / Dual 12-Bit
Flat Panel Display Interface
VT6103
VT8237R
V-Link
South Bridge
Figure 1. System Block Diagram
The complete chipset consists of the CN333 North Bridge and the VT8237R V-Link South Bridge. The CN333 integrates VIA’s
most advanced system controller with a high-performance UniChrome Pro 3D / 2D graphics / video controller plus flat panel and
DVI monitor. The CN333 provides superior performance between the CPU, DRAM, V-Link and integrated graphics controller
with pipelined, burst and concurrent operation. The VT8237R is a highly integrated peripheral controller which includes V-Link-
to-PCI / V-Link-to-LPC controllers, Ultra DMA IDE controller, USB2.0 host controller, 10/100Mb networking MAC, AC97 and
system power management controllers.
VIA C3 Processor Interface
The CN333 supports 133 / 100 MHz FSB VIA C3 processors and implements an eight-deep In-Order-Queue. VIA PowerSaver
technology is supported for VIA Antaur processors to reduce system power consumption while sustaining high processing power.
Memory Controller
The CN333 SDRAM controller supports up to two double-sided DDR333 / 266 DIMMs for 4 GB maximum physical memory.
The DDR DRAM interface allows zero-wait-state data transfer bursting between the DRAM and the memory controller’s data
buffers. The different banks of DRAM can be composed of an arbitrary mixture of 64 / 128 / 256 / 512 / 1024Mb DRAMs in x8 or
x16 configurations. The DRAM controller can run either synchronous or pseudo-synchronous with the host CPU bus.