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Data Sheet

CN333

North Bridge

with Integrated UniChrome

Pro 3D / 2D Graphics

Controller

Revision 1.0

January 5, 2005

VIA TECHNOLOGIES, INC.

Summary of content (79 pages)

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Data Sheet CN333 North Bridge with Integrated UniChrome Pro 3D / 2D Graphics Controller Revision 1.0 January 5, 2005 VIA TECHNOLOGIES, INC.
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Copyright Notice: Copyright © 2004-2005, VIA Technologies Incorporated. All Rights Reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise without the prior written permission of VIA Technologies Incorporated. The material in this document is for information only and is subject to change without notice.
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CN333 Data Sheet REVISION HISTORY Document Release 1.0 Date 1/5/05 Revision 1.
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CN333 Data Sheet TABLE OF CONTENTS REVISION HISTORY .......................................................................................................................................................................I TABLE OF CONTENTS.................................................................................................................................................................. II LIST OF FIGURES ...........................................................................................
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CN333 Data Sheet DEVICE 0 FUNCTION 2 REGISTERS – HOST CPU....................................................................................................................... 37 Device 0 Function 2 Header Registers ................................................................................................................................ 37 Device 0 Function 2 Device-Specific Registers ...................................................................................................................
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CN333 Data Sheet LIST OF FIGURES FIGURE 1. FIGURE 2. FIGURE 3. FIGURE 4. FIGURE 5. SYSTEM BLOCK DIAGRAM.................................................................................................................................... 5 INTEGRATED UNICHROME PRO GRAPHICS CONTROLLER INTERNAL BLOCK DIAGRAM ............ 7 BALL DIAGRAM (TOP VIEW) – FLAT PANEL / DIGITAL VIDEO OUTPUT................................................ 9 GRAPHICS APERTURE ADDRESS TRANSLATION..........................................
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CN333 Data Sheet CN333 NORTH BRIDGE 133 / 100 MHz VIA C3 Front Side Bus Integrated UniChrome Pro 3D / 2D Graphics and Video Controllers Advanced DDR333 SDRAM Controller 1 GB / Sec Ultra V-Link Interface PRODUCT FEATURES • Defines Highly Integrated Solutions for Full Featured, Power Efficient PC Designs – – – – • High Performance CPU Interface – – – • Supports 133 / 100 MHz FSB VIA C3 processors Eight outstanding transactions (eight-level In-Order Queue (IOQ)) Built-in Phase Lock Loop circuitry for op
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CN333 Data Sheet • Advanced System Power Management Support – – – – – – • ACPI 2.0 and PCI Bus Power Management 1.
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CN333 Data Sheet Video Acceleration High Quality Video Processor – RGB555, RGB565, RGB8888 and YUV422 video playback formats – High quality 5-tap horizontal and 5-tap vertical scaler (up or down) for both horizontal and vertical scaling (linear interpolation for horizontal and vertical p-scaling and filtering for horizontal and vertical down-scaling) – Independent graphics and video gamma tables – 2 sets of Color and Chroma Key support – Color enhancement for contrast, hue, saturation and brightness – Displ
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CN333 Data Sheet • Extensive Display Support for External Video Output – – – CRT display interface 12-bit Digital Video Port with support for external DVI transmitter 24-bit / Dual 12-Bit FPD interface to external LVDS transmitter CRT Display – – CRT display interface with 24-bit true-color RAMDAC up to 300 MHz pixel rate with gamma correction capability Supports CRT resolutions up to 1920 x 1440 12-Bit DVI Transmitter Interface – – – 1.
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CN333 Data Sheet CN333 SYSTEM OVERVIEW The CN333 is a high performance, cost-effective and energy efficient UMA North Bridge with integrated UniChrome Pro graphics / video controller used for the implementation of mobile and desktop personal computer systems with 133 / 100 MHz CPU host bus (“Front Side Bus”) based on VIA C3 processors.
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CN333 Data Sheet Ultra V-Link The CN333 North Bridge interfaces to the South Bridge through a high speed (up to 1 GB / Sec) 8x, 66 MHz Data Transfer interconnect bus called “Ultra V-Link”. Deep pre-fetch and post-write buffers are included to allow for concurrent CPU and VLink operation. The combined CN333 North Bridge and VT8237R South Bridge system supports enhanced PCI bus commands such as “Memory-Read-Line”, “Memory-Read-Multiple” and “Memory-Write-Invalid” commands to minimize snoop overhead.
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CN333 Data Sheet North Bridge Host Bus 66 MHz PCI Host Bus Interface VGAGFXController MPEGEngine Display Engine IGA 1 Panel Vertex Cache Setup Engine Texture Engine Rendering Pipelines VideoProcessor Texture Cache 3D Engine AGP-like Interface IGA 2 HWSprite HWCursor GFXStream Mux 128-bit2DEngine Digital Video Port CommandEngine 24-Bit FPD plus 12-Bit DVP Digital Video Port 1 DAC CRT VideoEngine 0/1 (Scaler/ YUV-to-RGB) Vide o Stream MemoryInterface Unit North Bridge Memory Controlle
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CN333 Data Sheet Desktop Modes for Single Display CRT Maximum Refresh Resolution 640x480 800x600 1024x768 1280x1024 1400x1050 1600x1200 1920x1440 BPP 60 75 85 100 120 8 √ √ √ √ √ 16 32 √ √ √ √ √ √ √ √ √ √ 8 16 32 √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ 8 √ √ √ √ 16 32 √ √ √ √ √ √ √ √ 8 16 32 √ √ √ √ √ √ √ √ √ 8 √ 16 32 √ √ 8 16 32 √ √ √ √ √ √1 √ √ √2 8 √ √ 16 √ √ 32 √ √ Table 1.
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CN333 Data Sheet PINOUTS Key 1 4 5 6 7 8 11 12 13 14 15 16 17 20 21 22 23 24 25 26 27 28 29 HD 28# HD 29# HD 25# HD 26# HD 16# HD 13# GND HD 5# HD 15# GND HA 23# HA 19# GND HA 11# BNR# NC GND DE FER# HREQ 0# GND D RDY# ADS# GND HD 34# GND HD 31# GND HD 24# HD 19# GND HD 10# HD 17# HD 4# NC HA 30# HA 31# HA 15# GND HA 4# NC B PRI# HREQ 2# HIT M# D BSY# RS2# NC HD 38# HD 22# NC HD 32# NC NC HD 20# HD 11# HD 12# NC HD 8# HD 6# HA
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CN333 Data Sheet Pin Lists Table 2.
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CN333 Data Sheet Table 3.
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CN333 Data Sheet Table 4.
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CN333 Data Sheet Pin Descriptions CPU Interface Pin Descriptions CPU Interface Signal Name Pin # I/O Signal Description HA[31:3]# (see pin list) IO HD[63:0]# ADS# BNR# (see pin list) A28 A21 IO IO IO BPRI# B23 IO DBSY# B26 IO DEFER# A24 IO DRDY# HIT# A27 E25 IO IO HITM# B25 I HLOCK# E24 I HREQ[4:0]# C23, D24, B24, IO C22, A25 HTRDY# D25 IO RS[2:0]# B27, C25, C26 IO CPURST# D16 O BREQ0# C27 O Host Address Bus. HA[31:3] connect to the address bus of the host CPU.
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CN333 Data Sheet The pinouts were defined assuming the ATX PCB layout model shown below (and general pin layout shown) as a guide for PCB component placement. Other PCB layouts (AT, LPX and NLX) were also considered and can typically follow the same general component placement.
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CN333 Data Sheet Ultra V-Link Pin Descriptions Ultra V-Link Interface Signal Name Pin # I/O Signal Description VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8 VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 VPAR VBE# UPCMD AK21 AG20 AK13 AJ13 AH20 AK20 AJ14 AH14 AF19 AH19 AH15 AF15 AF18 AH18 AG15 AH16 AF14 AG16 AG19 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I V-Link Data Bus.
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CN333 Data Sheet CRT and Serial Bus Pin Descriptions CRT Interface Signal Name AR AG AB HSYNC VSYNC RSET Pin # T3 T2 T1 V1 V2 V4 I/O AO AO AO O O AI Signal Description Analog Red. Analog red output to the CRT monitor. Analog Green. Analog green output to the CRT monitor. Analog Blue. Analog blue output to the CRT monitor. Horizontal Sync. Output to CRT. Vertical Sync. Output to CRT. Reference Resistor. Tie to GNDDAC through an external 82Ω 1% resistor to control the RAMDAC full-scale current value.
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CN333 Data Sheet Flat Panel Display Port (FPDP) Pin Descriptions The FPDP can be configured as either an LVDS transmitter interface port (see the LVDS Transmitter Interface) 24-Bit / Dual 12-Bit Flat Panel Display Interface Signal Name FPD23 / FPD0D11 FPD22 / FPD0D10 FPD21 / FPD0D09 FPD20 / FPD0D08 FPD19 / FPD0D07 FPD18 / FPD0D06 FPD17 / FPD0D05 FPD16 / FPD0D04 FPD15 / FPD0D03 FPD14 / FPD0D02 FPD13 / FPD0D01 FPD12 / FPD0D00 FPD11 / FPD1D11 FPD10 / FPD1D10 FPD09 / FPD1D09 FPD08 / FPD1D08 FPD07 / FPD1D07 FPD
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CN333 Data Sheet Digital Video Port 1 (GDVP1) Pin Descriptions GDVP1 can be configured as either a DVI transmitter interface port (see the DVI Transmitter Interface pin lists below for details).
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CN333 Data Sheet Clock, Reset, Power Control, GPIO, Interrupt and Test Pin Descriptions Clocks, Resets, Power Control, General Purpose I/O, Interrupts and Test Signal Name HCLK+ Pin # N5 I/O I HCLK– MCLKO N6 F30 I O MCLKI DISPCLKI F29 P2 I I DISPCLKO P3 O GCLK XIN P6 P7 I I RESET# AH21 I PWROK SUSST# AG21 AJ21 I I AGPBUSY# / NMI AE21 O GPOUT / CAPD14 GPO0 / CAPD15 U7 AA2 O O INTA# V5 O TCLK N7 I TESTIN# F27 I DFTIN# F28 I BISTIN / CAPAFLD U6 I Revision 1.
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CN333 Data Sheet Compensation and Reference Voltage Pin Descriptions Compensation Signal Name HRCOMP Pin # F13 I/O AI VLCOMPP AGPCOMPN AE14 AE2 AI AI AGPCOMPP AE1 AI Signal Description Power Plane Host CPU Compensation. Connect a 20.5 Ω 1% resistor to ground. VTT Used for Host CPU interface I/O buffer calibration. V-Link Compensation. Connect a 360 Ω 1% resistor to ground. VCC15VL AGP N Compensation. Connect a 60.4 Ω 1% resistor to VCC15AGP VCC15AGP. AGP P Compensation. Connect a 60.
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CN333 Data Sheet Power Pin Descriptions Analog Power / Ground Signal Name VCCA33HCK1 Pin # M1 I/O P GNDAHCK1 M2 P VCCA33HCK2 M4 P GNDAHCK2 M5 P VCCA33MCK GNDAMCK G28 G27 P P VCCA33GCK GNDAGCK M3 M6 P P VCCA15PLL1 GNDAPLL1 N3 N4 P P VCCA15PLL2 GNDAPLL2 P4 P5 P P VCCA15PLL3 GNDAPLL3 N1 N2 P P R4, U4 VCCA33DAC[1:2] R5, T4, U5 GNDADAC[1:3] P P Signal Description Power for Host CPU Clock PLL 1 (3.3V ±5%). 400 MHz for CPU / DRAM frequencies of multiples of 100, 133 and 200 MHz.
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CN333 Data Sheet Strap Pin Descriptions Strap Pins (External pullup / pulldown straps are required to select “H” / “L”) Actual Signal Strap Pin VD7 VT8235M-CD: SDCS3# VT8235M-CE: SDCS3# VT8237R: PDCS3# VD6 VT8235M-CD: SDA2 VT8235M-CE: SDA2 VT8237R: PDA2 VD5 VT8235M-CD: SDA1 VT8235M-CE: SDA1 VT8237R: PDA1 VD3 VT8235M-CD: SA19 VT8235M-CE: Strap_VD3 VT8237R: GPIOD VD2 VT8235M-CD: SA18 VT8235M-CE: Strap_VD2 VT8237R: GPIOB VD4, VD1, VD0 VT8235M-CD: SDA0, SA17, SA16 VT8235M-CE: SDA0, Strap_VD1, Strap_VD0 VT8237R
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CN333 Data Sheet REGISTERS Register Overview The following tables summarize the configuration and I/O registers of the CN333 North Bridge. These tables also document the power-on default value (“Default”) and access type (“Acc”) for each register. Access type definitions used are RW (Read/Write), RO (Read/Only), “—” for reserved / used (essentially the same as RO), RWC (or just WC) (Read / Write 1’s to Clear individual bits) and W1 (Write Once then Read / Only after that).
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CN333 Data Sheet Device 0 Function 0 Registers – AGP Header Registers Offset Configuration Space Header 1-0 Vendor ID 3-2 Device ID 5-4 Command 7-6 Status 8 Revision ID 9 Program Interface A Sub Class Code B Base Class Code C -reserved- (Cache Line Size) D Latency Timer E Header Type F -reserved- (Built In Self Test) 13-10 Graphics Aperture Base 14-2B -reserved2D-2C Subsystem Vendor ID 2F-2E Subsystem ID 30-33 -reserved37-34 Capability Pointer 38-3F -reserved- Device 0 Function 1 Registers – Error Reportin
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CN333 Data Sheet Device 0 Function 2 Registers – Host CPU Header Registers Offset 1-0 3-2 5-4 7-6 8 9 A B C D E F 10-2B 2D-2C 2F-2E 30-33 37-34 38-3F Configuration Space Header Vendor ID Device ID for Host CPU Bus Command Status Revision ID Program Interface Sub Class Code Base Class Code -reserved- (Cache Line Size) -reserved- (Latency Timer) -reserved- (Header Type) -reserved- (Built In Self Test) -reservedSubsystem Vendor ID Subsystem ID -reservedCapability Pointer -reserved- Revision 1.
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CN333 Data Sheet Device 0 Function 3 Registers – DRAM Header Registers Offset Configuration Space Header 1-0 Vendor ID 3-2 Device ID for DRAM Control 5-4 Command 7-6 Status 8 Revision ID 9 Program Interface A Sub Class Code B Base Class Code C -reserved- (Cache Line Size) D -reserved- (Latency Timer) E -reserved- (Header Type) F -reserved- (Built In Self Test) 10-2B -reserved2D-2C Subsystem Vendor ID 2F-2E Subsystem ID 30-33 -reserved37-34 Capability Pointer 38-3F -reservedDevice-Specific Registers Offset D
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CN333 Data Sheet Device 0 Function 4 Registers – Power Management Function 3 DRAM Device-Specific Registers (continued) Default Acc Offset Graphics Control B0 Graphics Control 1 00 RW B1 Graphics Control 2 00 RW B2 Graphics Control 3 00 RW B3 Graphics Control 4 00 RW B4 Graphics Control 5 00 RW B5-BF -reserved00 — Offset AGP Controller Interface Control C0 AGP Controller Interface Control C1-DF -reserved- Default 00 00 Acc RW — Offset E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0-FF Default 00 00 0
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CN333 Data Sheet Device 0 Function 7 Registers – V-Link / PCI Header Registers Offset Configuration Space Header 1-0 Vendor ID 3-2 Device ID for V-Link Control 5-4 Command 7-6 Status 8 Revision ID 9 Program Interface A Sub Class Code B Base Class Code C -reserved- (Cache Line Size) D -reserved- (Latency Timer) E -reserved- (Header Type) F -reserved- (Built In Self Test) 10-2B -reserved2D-2C Subsystem Vendor ID 2F-2E Subsystem ID 30-33 -reserved37-34 Capability Pointer 38-3F -reservedDevice-Specific Register
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CN333 Data Sheet Device 1 Registers - PCI-to-PCI Bridge Header Registers Offset 1-0 3-2 5-4 7-6 8 9 A B C D E F 13-10 14-17 18 19 1A 1B 1C 1D 1F-1E 21-20 23-22 25-24 27-26 28-33 34 35-3F Configuration Space Header Vendor ID Device ID Command Status Revision ID Program Interface Sub Class Code Base Class Code -reserved- (Cache Line Size) -reserved- (Latency Timer) Header Type -reserved- (Built In Self Test) Graphics Aperture Base -reservedPrimary Bus Number Secondary Bus Number Subordinate Bus Number -reser
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CN333 Data Sheet Miscellaneous I/O Configuration Space I/O One I/O port is defined: Port 22. All North Bridge registers (listed above) are addressed via the following configuration mechanism: Port 22 – PCI / AGP Arbiter Disable ..............................RW 7-2 Reserved ........................................ always reads 0 1 AGP Arbiter Disable 0 Respond to GREQ# signal .....................default 1 Do not respond to GREQ# signal 0 PCI Arbiter Disable 0 Respond to all REQ# signals.................
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CN333 Data Sheet Device 0 Function 0 Registers – AGP Offset 7-6 – Status (0210h)............................................ RWC 15 Detected Parity Error 0 No parity error detected......................... default 1 Error detected in either address or data phase. This bit is set even if error response is disabled (command register bit-6). ..... write one to clear 14 Signaled System Error (SERR# Asserted) ........................................always reads 0 13 Signaled Master Abort 0 No abort received ...
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CN333 Data Sheet Device 0 Function 0 Header Registers (continued) Offset E - Header Type (00h) ............................................RO 7-0 Header Type Code ..................Rx4F[0]=0: reads 00h: single function ...................Rx4F[0]=1: reads 80h, multi function Offset 13-10 - Graphics Aperture Base (AGP 3.0) (00000008h) ...................................................................... RW This register is interpreted per the following definition if Rx4D[2]=1 (AGP 3.0 header at Rx80h).
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CN333 Data Sheet AGP Miscellaneous Control AGP Power Management Control Offset 4F – Multiple Function Control (00h)..................RW 7-1 Reserved ........................................ always reads 0 0 Bridge Configuration Supports Multiple Functions 0 Not supported, other functions 1, 2, 3, 4 and 7 cannot be seen and will return FFFFFFFFh when accessed........................................default 1 Supported (this bit is reflected on Rx0E[7]) Offset 50 – Power Management Capability ID ...........
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CN333 Data Sheet AGP GART / Graphics Aperture Since address translation using the above scheme requires an access to system memory, an on-chip cache (called a “Translation Lookaside Buffer” or TLB) is utilized to enhance performance. The TLB in the CN333 contains 16 entries. Address “misses” in the TLB require an access of system memory to retrieve translation data. Entries in the TLB are replaced using an LRU (Least Recently Used) algorithm.
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CN333 Data Sheet Device 0 Function 1 Registers – Error Reporting Device 0 Function 1 Header Registers Offset 7-6 – Status (0200h)............................................ RWC 15 Detected Parity Error 0 No parity error detected......................... default 1 Error detected in either address or data phase. This bit is set even if error response is disabled (command register bit-6). ......... write 1 to clear 14 Signaled Sys Err (SERR# Asserted) .
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CN333 Data Sheet Device 0 Function 1 Device-Specific Registers These registers are normally programmed once at system initialization time. V-Link Error Reporting AGP Error Reporting Offset 50 – V-Link Error Status ......................................WC 7-1 Reserved ........................................ always reads 0 0 V-Link Parity Error Detected by NB................WC 0 No V-Link Parity Error Detected ...........
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CN333 Data Sheet Device 0 Function 2 Registers – Host CPU Device 0 Function 2 Header Registers Offset 7-6 – Status (0200h)............................................ RWC 15 Detected Parity Error 0 No parity error detected......................... default 1 Error detected in either address or data phase. This bit is set even if error response is disabled (command register bit-6). ..... write one to clear 14 Signaled Sys Err (SERR# Asserted) .always reads 0 13 Signaled Master Abort 0 No abort received .....
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CN333 Data Sheet Device 0 Function 2 Device-Specific Registers These registers are normally programmed once at system initialization time. Host CPU Control Offset 52 – CPU Interface Advanced Ctrl (00h) ............ RW 7 CPU RW DRAM 0WS for Back-to-Back Pipeline Access 0 Disable................................................... default 1 Enable 6 HREQ High Priority 0 Disable................................................... default 1 Enable 5 AGTL+ Pullups Default set from the inverse of the VD3 strap.
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CN333 Data Sheet Offset 56 – Reorder Latency (00h) .................................. RW 7-4 Medium Threshold for Write Policy to Improve Memory Read / Write Performance A setting of 2-4 is recommended ............. default = 0h 3-0 Maximum Reorder Latency 0000 Disable (same as Rx55[0]=0) ................
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CN333 Data Sheet Offset 5F – CPU Miscellaneous Control (00h) ............... RW 7 Same Bank But Different Sub-Bank Considered Off-Page 0 Disable................................................... default 1 Enable (reduces post-write burst length and may increase performance) 6 Back-to-Back Fast Read, Burst CPU-to-AGP Read and Burst CPU-to-Memory Read 0 Disable................................................... default 1 Enable 5 Machine Error Output 0 Disable.................................................
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CN333 Data Sheet Offset 66 – Burst DRDY Timing Control 1 (00h) .......... RW 7 Burst DRDY Wait State #8 6 Burst DRDY Wait State #7 5 Burst DRDY Wait State #6 4 Burst DRDY Wait State #5 3 Burst DRDY Wait State #4 2 Burst DRDY Wait State #3 1 Burst DRDY Wait State #2 0 Burst DRDY Wait State #1 0 0 ws DRDY Burst.................................. default 1 1 ws DRDY Burst Offset 60 – DRDY L Timing Control 1 (00h)..................RW 7-6 Phase 4 L Wait States ..........................
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CN333 Data Sheet Host CPU AGTL+ I/O Control Offset 75 – AGTL+ I/O Control (00h) ............................ RW 7 AGTL+ 1x Input Increase Delay to Filter Noise 0 Disable................................................... default 1 Enable 6 AGTL+ 2x Input Increase Delay to Filter Noise 0 Disable................................................... default 1 Enable 5 AGTL+ Slew Rate Control 0 Disable...................................................
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CN333 Data Sheet Device 0 Function 3 Registers – DRAM Device 0 Function 3 Header Registers Offset 7-6 – Status (0200h)............................................ RWC 15 Detected Parity Error 0 No parity error detected......................... default 1 Error detected in either address or data phase. This bit is set even if error response is disabled (command register bit-6). ..... write one to clear 14 Signaled Sys Err (SERR# Asserted) .always reads 0 13 Signaled Master Abort 0 No abort received .........
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CN333 Data Sheet Device 0 Function 3 Device-Specific Registers These registers are normally programmed once at system initialization time. DRAM Control These registers are normally set at system initialization time and not accessed after that during normal system operation.
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CN333 Data Sheet Offset 55 - DRAM Rank Decode Address Config (00h) RW 7-2 Reserved ........................................always reads 0 1-0 DRAM Rank Decode Address Configuration 00 .................................................... default 01 10 11 Offset 51-50 - DRAM MA Map Type (2222h) ................RW 15-13 Bank 5/4 MA Map Type (see Table below) 12 Bank 5/4 1T Command Rate 0 2T Command .........................................
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CN333 Data Sheet Offset 68 – DRAM DDR Control (00h)........................... RW 7 DRAM Access Timing 0 2T .................................................... default 1 3T 6 Non-Burst Write-to-Write Can Be Closer in NonDQM Mode 0 Disable................................................... default 1 Enable 5 Zero Delay DRAM Channel Switching for Read Cycles 0 Disable................................................... default 1 Enable 4 Zero Delay DRAM Channel Switching for Write Cycles 0 Disable............
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CN333 Data Sheet Offset 6B - DRAM Arbitration Control (10h)................ RW 7 DQS Input DLL Adjust 0 Disable................................................... default 1 Enable 6 DQS Output DLL Adjust 0 Disable................................................... default 1 Enable 5 Burst Refresh 0 Disable................................................... default 1 Enable 4 Reserved (Do Not Program) ................... default = 1 3 HA14 / HA22 Swap 0 Normal.................................................
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CN333 Data Sheet Offset 6E – DRAM Control (00h) ................................... RW 7 Reserved ........................................always reads 0 6 DRAM Scrubber 0 Disable................................................... default 1 Enable 5 DRAM Scrubber Redirect 0 Disable................................................... default 1 Enable 4-3 Reserved ........................................always reads 0 2 For Double-Sided DIMMs, Interleave Using Address Bit-15 0 Disable...........................
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CN333 Data Sheet Offset 78 – DRAM Timing Control (13h)....................... RW 7-6 Reserved (Do Not Program) .................... default = 0 5-4 Write MD / DQS / CAS Timing Range Control 00 01 ................................................... default 10 11 3-0 Reserved (Do Not Program) ................... default = 3 Offset 70 – DRAM DDR Control 1 (00h) ........................RW 7-0 Channel A DQS Output Delay 00h .....................................................
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CN333 Data Sheet Offset 7C – DIMM #0 DQS Input Delay Offset (00h) ... RW Values are programmed as two's-complement 7-5 Rank 1 DQS Input 2nd-Order Delay Offset 000 .................................................... default … 111 4-0 Rank 0 DQS Input Delay Offset 00000 .................................................... default … 11111 Offset 7A – DRAM DQS Capture Ctrl Chan A (44h)....RW 7-6 MD Input Internal Timing Control 00 01 ....................................................
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CN333 Data Sheet Table 9. 1x Bandwidth (64-Bit DDR) Memory Address Mapping Table MA: 64/128Mb 2K page 001 4K page 010 8K page 011 256/512Mb 2K page 101 4K page 110 8K page 111 1Gb 8K page 100 Revision 1.
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CN333 Data Sheet ROM Shadow Control Offset 82 – F-ROM Shadow /Memory Hole / SMI Control (00h) ................................................................................... RW 7-6 Reserved ........................................always reads 0 5-4 F0000h-FFFFFh 00 Read/write disable ................................. default 01 Write enable 10 Read enable 11 Read/write enable 3-2 Memory Hole 00 None ....................................................
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CN333 Data Sheet DRAM Above 4G Control Offset 86 – SMM / APIC Decoding (01h) ....................... RW 7-6 Reserved ........................................always reads 0 5 APIC Lowest Interrupt Arbitration 0 Disable................................................... default 1 Enable 4 I/O APIC Decoding 0 FECxxxxx accesses go to PCI ...............
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CN333 Data Sheet UMA Control Offset A4 – Graphics Miscellaneous Control (00h) ....... RW 7-4 Reserved ........................................always reads 0 3 AGP DIO (Pad) Clock 0 Disable................................................... default 1 Enable 2 Graphics Data Delay to Sync with Clock 0 No sync.................................................. default 1 Sync with clock 1-0 Graphics DISPCLK Delay Control 00 ....................................................
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CN333 Data Sheet Graphics Control AGP Controller Interface Control Offset B0 – Graphics Control 1 (00h)..............................RW 7-4 Reserved ........................................ always reads 0 3 Frame Buffer Rank Searching 0 Automatic...............................................default 1 Select bank per bits 2-0 2-0 Frame Buffer Rank Location Offset C0 – AGP Controller Interface Control (00h) .... RW 7-3 Reserved ........................................
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CN333 Data Sheet DRAM Drive Control Offset E6 – Drive Group S-Port Control (00h) .............. RW 7 DQ S-Port Control ................................... default = 0 6 CS S-Port Control .................................... default = 0 5 MAA S-Port Control................................ default = 0 4 MAB S-Port Control ................................ default = 0 3 DQS S-Port Control ................................. default = 0 2-1 Reserved ........................................
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CN333 Data Sheet Device 0 Function 4 Registers – Power Management Device 0 Function 4 Header Registers All registers are located in PCI configuration space. They should be programmed using PCI configuration mechanism 1 through CF8 / CFC with bus number and device number equal to zero and function number equal to 4. Offset 1-0 - Vendor ID (1106h) .........................................RO 15-0 ID Code (reads 1106h to identify VIA Technologies) Offset 3-2 - Device ID for Power Manager (4259h).........
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CN333 Data Sheet Device 0 Function 4 Device-Specific Registers These registers are normally programmed once at system initialization time. Power Management Control Offset A0 – Power Management Mode (00h)..................RW 7 Dynamic Power Management 0 Disable ...................................................default 1 Enable 6 Halt / Shutdown Power Management 0 Disable ...................................................default 1 Enable 5 Stop Clock Power Management 0 Disable ..............................
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CN333 Data Sheet Device 0 Function 7 Registers – V-Link Device 0 Function 7 Header Registers Offset 7-6 – Status (0200h)............................................ RWC 15 Detected Parity Error 0 No parity error detected......................... default 1 Error detected in either address or data phase. This bit is set even if error response is disabled (command register bit-6). ..... write one to clear 14 Signaled Sys Err (SERR# Asserted) .always reads 0 13 Signaled Master Abort 0 No abort received .......
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CN333 Data Sheet Device 0 Function 7 Device-Specific Registers These registers are normally programmed once at system initialization time. V-Link Control Offset 45 –NB V-Link Bus Timer (44h).......................... RW 7-4 Timer for Normal Priority Requests from SB 0000 Immediate 0001 1*4 VCLKs 0010 2*4 VCLKs 0011 3*4 VCLKs 0100 4*4 VCLKs............................................
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CN333 Data Sheet Offset 48 – NB/SB V-Link Configuration (18h)............. RW 7 V-Link Parity Check 0 Disable................................................... default 1 Enable 6 Reserved ........................................always reads 0 5 16-bit Bus Width Supported 0 Not Supported........................................ default 1 Supported 4 8-Bit Bus Width Supported 0 Not Supported 1 Supported ............................................. default 3 4x Rate Supported 0 Not Supported 1 Supported .....
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CN333 Data Sheet Offset 4E – CCA Master Priority (00h).......................... RW 7 1394 High Priority 0 Low priority........................................... default 1 High priority 6 LAN / NIC High Priority 0 Low priority........................................... default 1 High priority 5 Reserved ........................................always reads 0 4 USB High Priority 0 Low priority........................................... default 1 High priority 3 Reserved ......................................
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CN333 Data Sheet PCI Bus Control These registers are normally programmed once at system initialization time. Offset 73 - PCI Master Control (00h) ............................. RW 7 Reserved ........................................always reads 0 6 PCI Master 1-Wait-State Write 0 Zero wait state TRDY# response........... default 1 One wait state TRDY# response 5 PCI Master 1-Wait-State Read 0 Zero wait state TRDY# response........... default 1 One wait state TRDY# response 4 WSC# 0 Disable....................
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CN333 Data Sheet Offset 76 - PCI Arbitration 2 (00h) ................................. RW 7 I/O Port 22 Access 0 CPU access to I/O address 22h is passed on to the PCI bus ............................................ default 1 CPU access to I/O address 22h is processed internally 6 Reserved ........................................always reads 0 5-4 Master Priority Rotation Control 00 Disable...................................................
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CN333 Data Sheet Graphics Aperture Control V-Link CKG Control Offset 85-84 – Graphics Aperture Size (0000h)..............RW 15-12 Reserved ........................................ always reads 0 11-0 Graphics Aperture Size [31:20] .......... default = 00h 111100111111 4MB 111100111110 8MB 111100111100 16MB 111100111000 32MB 111100110000 64MB 111100100000 128MB 111100000000 256MB 111000000000 512MB 110000000000 1GB 100000000000 2GB <= Max supported 000000000000 4GB <= Do not program In AGP 2.
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CN333 Data Sheet V-Link Compensation / Drive Control VT8237R South Bridge: Offset B4 – V-Link NB Compensation Control (00h) ....RW 7-5 V-Link Autocomp Output Value – High Drive . RO 4 Reserved ........................................ always reads 0 3-1 V-Link Autocomp Output Value – Low Drive.. RO 0 Compensation Select 0 Auto Comp (use values in bits 7-5, 3-1) default 1 Manual Comp (use values in RxB5, B6) Offset B8 – V-Link SB Compensation Control (00h) ....
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CN333 Data Sheet Device 1 Registers – PCI-to-PCI Bridge Device 1 Header Registers Device 1 Offset 7-6 - Status (Primary Bus) (0230h) .... RWC 15 Detected Parity Error ........................always reads 0 14 Signaled System Error (SERR#).......always reads 0 13 Signaled Master Abort 0 No abort received .................................. default 1 Transaction aborted by the master with Master-Abort (except Special Cycles).............. .......................................
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CN333 Data Sheet Device 1 Offset 13-10 – Graphics Aperture Base (0000 0008h).................................................................................RW This register is interpreted per the following definition if RxFD[1]=1 (AGP 2.0 registers enabled). Device 1 Offset 1F-1E - Secondary Status ....................... RO 15-0 Secondary Status Rx44[4] = 0: these bits read back 0000h Rx44[4] = 1: these bits read back same as Rx7-6 31-22 Programmable Base Address Bits ..................
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CN333 Data Sheet Device 1 Device-Specific Registers AGP Bus Control Device 1 Offset 41 - CPU-to-AGP Flow Control 2 (08h) RW 7 Retry Status 0 No retry occurred................................... default 1 Retry Occurred ........................write 1 to clear 6 Retry Timeout Action 0 No action taken except to record status ....... def 1 Flush buffer for write or return all 1s for read 5-4 Retry Count 00 Retry 2, backoff CPU ............................
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CN333 Data Sheet Power Management Device 1 Offset 43 - AGP Master Latency Timer (22h) RW 7-4 Host to AGP Time slot 0 Disable (no timer) 1 16 GCLKs 2 32 GCLKs ..............................................default … … F 128 GCLKs 3-0 AGP Master Time Slot 0 Disable (no timer) 1 16 GCLKs 2 32 GCLKs ..............................................default … … F 128 GCLKs Device 1 Offset 70 – Capability ID (01h) ......................... RO 7-0 Capability ID ..................................
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CN333 Data Sheet ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Table 11. Absolute Maximum Ratings Symbol TC Parameter Case operating temperature Min Max Unit 0 85 oC Notes 1 1 TS Storage temperature –55 125 oC VIN Input voltage –0.5 VRAIL + 10% Volts 1, 2 Output voltage –0.5 VRAIL + 10% Volts 1, 2 VOUT Note 1. Stress above the conditions listed may cause permanent damage to the device.
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CN333 Data Sheet MECHANICAL SPECIFICATIONS 29.00 REF. 2.00*45º (4X) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 HEAT SLUG Ø 22.5 ~ 23.5 Ø 0.30 M C A S B S Ø 0.50 M C D S E S CN333 YYWWVV TAIWAN C ○ M LLLLLLLLLL ○ AB AD AF AH AK AA AC AE AG AJ Ø 0.10 M C Ø 0.25 M C A M B M Ø 0.50~0.70 (681X) JEDEC Spec MS-034 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1.
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CN333 Data Sheet 29.00 REF. 2.00*45º (4X) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 HEAT SLUG Ø 22.5 ~ 23.5 Ø 0.30 M C A S B S Ø 0.50 M C D S E S CN333 Country of Assembly Indicates Lead-Free Package AB AD AF AH AK AA AC AE AG AJ Ø 0.10 M C Ø 0.25 M C A M B M Ø 0.50~0.70 (681X) JEDEC Spec MS-034 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1.