Technical data

Analog Integrated Circuit Device Data
Freescale Semiconductor 19
908E621
TIMING DIAGRAMS
Figure 7. LIN Timing Measurements for Slow Slew Rate
Figure 8. Wake-Up Stop Mode Timing
Figure 9. Wake-Up Sleep Mode Timing
t
DOM-MIN
t
DOM-MAX
t
RL
TXD
LIN
RXD
V
LIN
t
RH
t
REC-MIN
t
REC-MAX
61.6% V
SUP
40% V
SUP
25.1% V
SUP
38.9% V
SUP
60% V
SUP
77.8% V
SUP
IRQ_A
LIN
Vrec
TpropWL Twake
Dominant level
0.4VSUP
t
PROPWL
t
WAKE
Dominant Level
0.4 V
SUP
V
LIN_REC
VDD
LIN
Vrec
TpropWL Twake
Dominant level
0.4VSUP
V
LIN_REC
0.4 V
SUP
Dominant Level
t
PROPWL
t
WAKE