User`s manual

Chapter 4
38
4.4.3 CHIPSET FEATURES SETUP MENU
ROM ISA BIOS (2C4I9G30)
CHIPSET FEATURES SETUP
AWARD SOFTWARE, INC.
Auto Configuration : Enabled
AT Bus Clock : 1/5CLK
Hidden Refresh : Enable
L2 Cache Scheme : Write Back
L1 Cache Scheme : Write Back
Cache Burst Read : 2T
Cache Write Cycle : 3T
System Shadow : Non-Cacheable
Video Shadow : Non-Cacheable
Fast Reset Emulation: Enable
Fast Reset Latency : 2 us
Latch Local Bus : T3
Local Bus Ready : Synchronize
ESC: Quit : Select Item
F1: Help PU/PD/+/-: Modify
F5: Old Values (Shift)F2: Color
F6: Load BIOS Defaults
F7: Load Setup Defaults
Fig 11: Default Setting for Cx486DX 40MHz CPU
Note:
1) the following table shows the settings for different CPU
Support: -
System Clock Freq.
20MHz 25MHz 33MHz 40MHz 50MHz
CPU Internal Clock Freq.
x1 x1/x2/x3 x1/x2/x3 x1/x2 x1
AT Bus Clock 1/3CLK 1/3CLK 1/4CLK 1/5CLK 1/6CLK
Cache Burst Read 1T 1T 2T 2T 2T
Cache Burst Write 2T 2T 2T 3T 3T
2) The option "L1 Cache Scheme" is shown only when the
Cyrix Cx486S/Cx486DX/DX2 CPUs are used.